Resources Contact Us Home
Semiconductor memory device having test pattern generating circuit

Image Number 2 for United States Patent #4821238.

A semiconductor memory device comprises an internal circuit including a memory circuit; a test pattern generating circuit; an element for receiving external signals supplied from the outside; and an input switching circuit connected between the test pattern generating circuit and the receiving element, for switching the input supplied to the internal circuit between output signals generating from the test pattern generating circuit and the external signals, the output signals generated from the test pattern generated circuit being input to the internal circuit through the input switching circuit in a test mode, the external signals being input to the internal circuit through the input switching circuit in a usual mode; the test pattern generating circuit, the input switching circuit, and the internal circuit being provided on the same chip.

  Recently Added Patents
High damage threshold frequency conversion system
Active matrix substrate, method for manufacturing same, and liquid crystal display apparatus
Storage apparatus and storage apparatus management method performing data I/O processing using a plurality of microprocessors
Clock face
Interconnecting virtual domains
Fan guide
Preserving user applied markings made to a hardcopy original document
  Randomly Featured Patents
Unsaturated polyester resin compositions
Setting device for a carding engine
Relief valve
Method and device for indicating a referee signal
Display context switching arrangement
Procedure for rapid thermal annealing of implanted semiconductors
Management of electrically driven engine accessories
Sensor for measuring material properties
Small vehicle lift