Resources Contact Us Home
Semiconductor memory device having test pattern generating circuit

Image Number 2 for United States Patent #4821238.

A semiconductor memory device comprises an internal circuit including a memory circuit; a test pattern generating circuit; an element for receiving external signals supplied from the outside; and an input switching circuit connected between the test pattern generating circuit and the receiving element, for switching the input supplied to the internal circuit between output signals generating from the test pattern generating circuit and the external signals, the output signals generated from the test pattern generated circuit being input to the internal circuit through the input switching circuit in a test mode, the external signals being input to the internal circuit through the input switching circuit in a usual mode; the test pattern generating circuit, the input switching circuit, and the internal circuit being provided on the same chip.

  Recently Added Patents
Toy ball
Look up table (LUT) structure supporting exclusive OR (XOR) circuitry configured to allow for generation of a result using quaternary adders
Handover signaling in wireless networks
Image correction method
Optimization of packaging sizes
Method and apparatus for variable accuracy inter-picture timing specification for digital video encoding
Stable nanoemulsions for ultrasound-mediated drug delivery and imaging
  Randomly Featured Patents
Lithographic apparatus and device manufacturing method
Organopolysiloxane polyesters
Method and apparatus for control of fluorescent lamps
Power de-rating reduction in a transmitter
Germicidal detergent packet
Method for recovering aluminium from materials containing metallic aluminium
System and method for building a target operating system from a source operating system
Hypericum plant named `Esm Cho`
Micro-dot ink jet recorder