Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Semiconductor memory device and array










Image Number 6 for United States Patent #4813017.

A memory array fabricated on a silicon substrate consists of memory cells each having two lateral p-n-p load-injector transistors and two vertical n-p-n flip-flop transistors with the p-n-p's being formed in a portion of the substrate which is electrically isolated from portions of the substrate in which the n-p-n's are formed. The layout of this cell, which is about as compact as a standard IIL memory cell, resulsts in the bases of the p-n-p's being electrically isolated from the emitters of the n-p-n's. This allows the p-n-p's to be operated in a linear region during critical operating times and thus limits stability problems associated with IIl memory cells while providing faster access times and a better tradeoff between read out currents and power dissipation.








 
 
  Recently Added Patents
Method and apparatus for reacquiring lines in a cache
Radiation detector array
Method and system for tracking mobile electronic devices while conserving cellular network resources
(4929
Tree drain grate
Monitoring cloud-runtime operations
Self-assembling surface coating
  Randomly Featured Patents
Arrangement for mechanical coupling of a driver to a coupling site of the ossicular chain
RF connector having a compliant contact
Soil-resistant coating for glass surfaces
Hole saw plug ejector
Steam bath apparatus and liquid or steam treatment equipment
Combination of ceiling fan bracket and motor casing
Plan-per-tuple optimizing of database queries with user-defined functions
Digital media processor
Method and system for data dispatch
Transportation system operation using identification codes