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Semiconductor memory device and array

Image Number 6 for United States Patent #4813017.

A memory array fabricated on a silicon substrate consists of memory cells each having two lateral p-n-p load-injector transistors and two vertical n-p-n flip-flop transistors with the p-n-p's being formed in a portion of the substrate which is electrically isolated from portions of the substrate in which the n-p-n's are formed. The layout of this cell, which is about as compact as a standard IIL memory cell, resulsts in the bases of the p-n-p's being electrically isolated from the emitters of the n-p-n's. This allows the p-n-p's to be operated in a linear region during critical operating times and thus limits stability problems associated with IIl memory cells while providing faster access times and a better tradeoff between read out currents and power dissipation.

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