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Integrated Hall element and amplifier with controlled offset voltage

Image Number 4 for United States Patent #4709214.

An integrated circuit includes an epitaxial layer. In a near central region thereof is formed a symmetrical array of four equal sized Hall cells that are connected in parallel to form one Hall element. A moat surrounds the Hall element consisting of two concentric isolation walls separated by a band of opposite conductivity epitaxial material. The output of the Hall element is connected to the input of an adjacent differential amplifier that has two extraordinarily large amplifying transistors with emitter areas each equal to about a half of a Hall area, for achieving much better control over the relative dimensions of these emitters and thus over the amplifier offset voltage from chip to chip. The emitter resistors are likewise made very wide and both pairs of components are physically arranged to have balanced thermal coupling to the Hall element for further enhancing control of offset voltage.

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