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Inverting logic buffer BICMOS switching circuit using an enabling switch for three-state operation with reduced dissipation










Image Number 5 for United States Patent #4678943.

A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN. Under this condition, the output terminal OUT is in a floating state. Thus, the switching circuit is a tri-state circuit.








 
 
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