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Process for fabricating a semiconductor device

Image Number 3 for United States Patent #4654113.

A method of forming an insulating layer having a planar surf on a lower wiring layer having given patterns steps at the shoulders of the patterns. On a lower wiring layer, a lower insulating layer is formed and a heat resistive material is coated over the lower insulative layer to form a substantially a planar top surface and to fill cavities appearing in the surface of the lower insulating layer with the material. Then, etching is carried out to preserve the profile of the surface of the coating layer and to remove the coating layer at portions where through-holes are to be formed. Any cavities in the surface of the lower insulating layer remain filled with the material after etching. An upper insulating layer is deposited on the exposed lower insulating layer and the remaining part of the coating layer. Through-holes and an upper wiring layer of given patterns are formed so that the upper wiring layer has no contact with the remaining part of the coating layer and so that the remaining part of the coating layer is never externally exposed.

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