Image Number 5 for United States Patent #4616346.
In a memory selectively operable in an active and a standby mode, a first oscillation signal of a first frequency is produced by an oscillator (35a or 35b) in the standby mode so as to reduce electric power consumption, instead of a second oscillation signal which is produced in the active mode and which has a second frequency higher than the first frequency. The first and the second oscillation signals are selectively supplied as a substrate voltage to a substrate (20) through a substrate voltage production circuit (36). The oscillator may comprise a first circuit portion (46 to 48) for oscillating the second oscillation signal and a capacitor circuit (51 to 53) connected to the first circuit portion through a second circuit portion (56 to 58) in the standby mode so as to generate the second oscillation signal. Alternatively, the oscillator comprises first and second oscillator sections (61 and 67) for generating the first and the second oscillation signals and a selecting circuit (70) for selecting the first and the second oscillation signals. The second oscillation circuit is kept inactive during generation of the first oscillation signal.