Image Number 3 for United States Patent #4485347.
The disclosed FSK demodulator includes a digital PLL for converting an FSK modulated input signal with two different frequencies to rectangular waveforms having durations as determined by those frequencies, two reversible N bit counters for counting clock pulses to determine instantaneous duty factors in the form of N parallel bits of the waveforms for each pulse repetition period, and a read only memory for multiplying alternate outputs, except for the sign bit, from the counters by a ratio of the lower to the higher frequency of the input signal. Then, a digital first-order low-pass filter removes a high frequency component from the output of the read only memory, resulting in a demodulated binary signal. The binary signal may be produced by setting or resetting a FLIP-FLOP when the sign bit from each of the counters is respectively a binary ONE or ZERO. Alternatively, another reversible M bit counter (when M>N) may count the clock pulses to equal the output from the read only memory.