Image Number 3 for United States Patent #4346458.
Monolithically integrated storage arrangement with storage cells arranged in a matrix and consisting of two cross-coupled I.sup.2 L structures (T1, T2 and T1', T2') each in the manner of a flip-flop, wherein the read signal is derived from the charge carrier current reinjected into the injection zone (P1 or P1') of the respective conductive inverting transistor (T1 or T1') and thus into the connected bit line (BL0, BL1). The storage cells of a matrix line are selected via a common address line (X) coupled to the emitters (N1, N1') of the inverting transistors (T1, T1') of said storage cells.In spite of the fact that the structures have minimum area requirements, a high read signal is obtained by subdividing the address line (X) into two partial word lines (X1, X2). One partial word line (X1) is connected to all emitters (N1) of the inverting transistors (T1) of one I.sup.2 L structure of all storage cells of a matrix line. The other partial word line (X2) is correspondingly connected to the emitters (N1') of the inverting transistors (T1') of the respective other I.sup.2 L structure of the storage cells of the matrix line. Subsequent to a group of storage cells, each of the two partial address lines (X1, X2) is connected to the common address line (X) via a resistor (RX).