Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Self-aligned double polysilicon MOS fabrication










Image Number 7 for United States Patent #4317690.

A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.








 
 
  Recently Added Patents
Masking method and apparatus
Plants and seeds of hybrid corn variety CH260114
Intralevel conductive light shield
Soybean cultivar BY0811143
Vertical gate LDMOS device
Circuit and method for generating an AC voltage from a plurality of voltage sources having a temporally variable DC output voltage
Wireless control system for a patient support apparatus
  Randomly Featured Patents
Microwave detection of soot content in a particulate trap
Wireless communication device, wireless communication system, and wireless communication method
Contextual presentation on electronic catalog pages of information reflective of prior orders
Method, system and computer-readable media for repairing data record corruption
Coupling for inserting a soaking bar into a blast furnace tap hole
Static type semiconductor memory device that can suppress standby current
Shoulder brace
Method and mechanism for the supersonic separation of droplets from a gas stream
Check accepting and cash dispensing automated banking machine system and method
Transient processing mechanism for power converters