Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Self-aligned double polysilicon MOS fabrication










Image Number 7 for United States Patent #4317690.

A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.








 
 
  Recently Added Patents
Pixel structure of a solid-state image sensor employing a charge sorting method
Systems and methods for detailed error reporting in data storage systems
Antagonists of the glucagon receptor
Stroboscopic light source for a transmitter of a large scale metrology system
Molded surface of a concrete product
Web development environment that enables a developer to interact with run-time output presentation of a page
Biological analysis arrangement and approach therefor
  Randomly Featured Patents
Reclosable, tamper-evident plastic lid for a container having a circular wall
Method and apparatus for border gateway protocol route management and routing policy modeling
Method for forming a tunnel intersecting a straight cruciate ligament tunnel
Quick release for sector plate
Specification method and apparatus for coding and decoding
Electrical connector assembly, plug, and socket
Receptor that binds IL-17
Electro-static sheet feeding method and apparatus
Reflective-transmissive type liquid crystal display device and method for fabricating the same
Surgical staple with augmented compression area