Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Self-aligned double polysilicon MOS fabrication










Image Number 7 for United States Patent #4317690.

A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.








 
 
  Recently Added Patents
System and transceiver clocking to minimize required number of reference sources in multi-function cellular applications including GPS
Artifact removal in nuclear images
Hand sign
Incrementally increasing deployment of gateways
Adjustable box extender
Medical device arm
Apparatus and methods for inventory, sale, and delivery of digitally transferable goods
  Randomly Featured Patents
Splitting device
Spinal fixation implant for mounting to spinous processes and related method
CMOS transistor with amorphous silicon elevated source-drain structure and method of fabrication
Printer page composition with color and text
Mold process for syndiotactic polypropylene
Window buck and methods of assembly
Photographic apparatus
Hydraulic drive with several hydraulic consumers also comprising a differential cylinder
Microfluidic particle-analysis systems
Method for managing a home equity sales program