Resources Contact Us Home
Self-aligned double polysilicon MOS fabrication

Image Number 7 for United States Patent #4317690.

A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.

  Recently Added Patents
Identifying a wireless network device across factory resets
Paging apparatus and method in a mobile communication system providing multimedia broadcast service
Optical device and image pickup device and image pickup system using the same
Optical sensor
System and method for completion optimization
Refresh of non-volatile memory cells based on fatigue conditions
Sword-shaped toy
  Randomly Featured Patents
Process for the preparation of cyanohydrin esters
Vitronectin receptor antagonist pharmaceuticals
Phlox plant named `Natural Feelings`
High/low flow anesthetic vaporizer
Motor protector particularly useful with hermetic electromotive compressors
Forming isolation regions for integrated circuits
Surface discharge type plasma panel divided into a plurality of sub-screens
Powder chalk line dispenser with demounted chalk reservoir
Network analyzer applying loss compensation using port extensions and method of operation
Add-on extension ladder