Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Self-aligned double polysilicon MOS fabrication










Image Number 7 for United States Patent #4317690.

A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.








 
 
  Recently Added Patents
Washing machine
Wake-up radio system
Secure device sharing
Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
(4934
Virtual image display device and manufacturing method of virtual image display device
Image processing device and information storage medium including motion vector information calculation
  Randomly Featured Patents
Product dispensing system
Automatic winding machine for tape-like articles
Swing seat assembly
Extended nip press apparatus
Method, apparatus and computer program providing signaling of zero/full power allocation for high speed uplink packet access (HSUPA)
Resilient bollard with rotatable collar for alerting vehicles of their location
Flush/recessable junction device
Method of sharing a memory between a browser mode and a video mode to reduce memory usage in a video system
Torque sensor and method of manufacturing torque sensor
Physical exerciser