Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Balanced input buffer circuit for semiconductor memory










Image Number 2 for United States Patent #4280070.

A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.








 
 
  Recently Added Patents
Wound dressing with a discontinuous contact layer surface
Microporous membranes and methods for producing and using such membranes
Host route convergence based on sequence values
Display screen with graphical user interface
Summarization of short comments
Laser protection polymeric materials
Machine tool with an electrical generator for passive power generation
  Randomly Featured Patents
Cuff-forming vein strap
Pass-through write policies of files in distributed storage management
Light emitting diode with phosphor material and reflective layer and method for making same
Apparatus and method for connecting wireless devices
Chemical vapor deposition of aluminum oxide
Apparatus for safely generating and dispensing a gas
Control apparatus, electronic device and signal processing apparatus
Curry comb
Method for computing borehole geometry from ultrasonic pulse echo data
Method and apparatus for enhanced CMP planarization using surrounded dummy design