Resources Contact Us Home
Balanced input buffer circuit for semiconductor memory

Image Number 2 for United States Patent #4280070.

A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.

  Recently Added Patents
Method and apparatus for over-the-air activation of neighborhood cordless-type services
Content display monitor
Neurophysiological central auditory processing evaluation system and method
Viewing stand
Produce container and lid assembly
Apparatus and method of managing radio bearer in wireless communication system
  Randomly Featured Patents
Linerless label tracking system
Curable mixtures containing N-sulfonylaminosulfonium salts as cationically active catalysts
Analog-to-digital converter utilizing vernier techniques
Gaming terminal
Fountain dryer unit
Gaming device having an award offer and termination bonus scheme
Methods of forming non-volatile memory devices having trenches
Motor terminal device
Cleansing of contaminants from gramophone records
Apparatus and method for detecting obstacles