Resources Contact Us Home
Balanced input buffer circuit for semiconductor memory

Image Number 2 for United States Patent #4280070.

A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.

  Recently Added Patents
Manufactured product configuration
Interface circuit and interface system
Lateral flow test kit and method for detecting an analyte
Image-processing method and program, and image-processing apparatus
Housekeeping cart
Method and apparatus for supporting management actions for very high throughput in wireless communications
  Randomly Featured Patents
Method and composition for the removal of phenolic resin coatings from aluminum
Image scanner
Method of making continuous filament web with statistical filament distribution
Antifriction bearing with pulse ring for measurement of speed rotation
Offset cancellation and slice adjust amplifier circuit
Drier information system
Reduction of errors during computation of inverse discrete cosine transform
Process for the preparation of a concentrated aqueous reactive dyestuff solution: triphenyl-dioxazine dyes, lithium salts
Paintable, surface-damage resistant compounded grade thermoplastic olefin (TPO)
Chemical oxygen generator