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Apparatus for scaling memory addresses

Image Number 4 for United States Patent #4234934.

Apparatus for scaling addresses received by a memory module in a modular requestor-memory system in which standard memory modules may be of a discretely variable size and utilized in a plurality of positions in an overall contiguous memory addressing scheme. In particular, this scaling apparatus enables a modular memory which is only partially populated, i.e., only able to respond to a subset of the set of all addresses available, to be located in any one of several positions representing different addressing ranges. This is accomplished without modification of the memory module itself. The memory module knows its discrete capacity, or size, by virtue of the population of the memory array storage locations (array cards) contained therein. The memory module then uses this information to scale, or strip off, the appropriate number of bits from the gross address to allow addressing of the restricted number of memory locations present in the memory module.

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