Image Number 8 for United States Patent #4141305.
A logic circuit generates in succession the stitch-control data for the successive stitches of a selected stitch pattern. The logic circuit does not store simultaneously all the stitch-control data for all the stitches of all the selectable stitch patterns, in the way done by conventional addressable random-access stitch-pattern memories. Instead, the logic circuit assumes successive states, in response to successive machine-synchronized pulses. In each state it generates, in the sense of bringing into existence for the first time, stitch-control data for the next stitch to be produced, this stitch-control data being derived from data related to a preceding stitch, e.g., the stitch-control data for the preceding stitch. The number of logic elements needed is low compared to that needed for a random-access stitch-pattern memory of the type storing all the stitch-control data for all the stitches of all the selectable patterns.