Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Electronic pattern control for a sewing machine










Image Number 7 for United States Patent #4141305.

A logic circuit generates in succession the stitch-control data for the successive stitches of a selected stitch pattern. The logic circuit does not store simultaneously all the stitch-control data for all the stitches of all the selectable stitch patterns, in the way done by conventional addressable random-access stitch-pattern memories. Instead, the logic circuit assumes successive states, in response to successive machine-synchronized pulses. In each state it generates, in the sense of bringing into existence for the first time, stitch-control data for the next stitch to be produced, this stitch-control data being derived from data related to a preceding stitch, e.g., the stitch-control data for the preceding stitch. The number of logic elements needed is low compared to that needed for a random-access stitch-pattern memory of the type storing all the stitch-control data for all the stitches of all the selectable patterns.








 
 
  Recently Added Patents
Browsing or searching user interfaces and other aspects
Scaleable status tracking of multiple assist hardware threads
Etching method, etching apparatus, and computer-readable recording medium
Data security for dynamic random access memory using body bias to clear data at power-up
Device, system, and method for logging near field communications tag interactions
Bio-stimulant for improved plant growth and development
Event-triggered server-side macros
  Randomly Featured Patents
Quantity controlled, fluent material dispensing apparatus
Bowling ball abrader and polisher system and method
Plasma-jet imaging apparatus and method
CMOS image sensor and method of manufacturing thereof
Laser scanning microscope system and scanning unit applied to the system
Hole-based ultra-deep photodiode in a CMOS image sensor and a process thereof
Process for preparing modified pigments
Method and apparatus for optimum channel assignment
Method for generating nanostructures and device for generating nanostructures
Layout of network using parallel and series elements