Image Number 2 for United States Patent #4136335.
A semiconductor charge coupled device (CCD) is provided with an array of auxiliary charge storage sites of successively decreasing binary digital storage capacities (1/2, 1/4, 1/8, 1/16, etc.) along the CCD propagation direction. These auxiliary sites sequentially subtract, from a propagating analog signal charge packet, successive amounts of charge ("1") vs. no charge ("0") corresponding to the presence vs. absence of correspondingly sufficient charge in the propagating analog packet. The resulting sequence of "1"'s and "0"'s provides a digital representation in the binary system of the analog signal charge packet.