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Digital phase-lock loop systems for phase processing of signals










Image Number 3 for United States Patent #3936762.

A digital phase-locked loop in which an error signal representing the difference between the phases of an input signal and an output signal is converted to a digital signal having a time-varying value. A programmable divider means is provided to produce a pulse control signal having a frequency which varies in accordance with the time-varying value of the digital signal. The pulse control signal controls the number of pulses which are deleted from a reference clock signal to produce an intermediate signal which in turn is fed to a feedback counter for producing the output signal, the phase of which depends on the number of deleted pulses, so that the phase of the output signal effectively follows the phase of the input signal.








 
 
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