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Scannable light emitting diode array and method

Image Number 2 for United States Patent #3932927.

There is disclosed a method of manufacturing the foregoing which comprises placing an epitaxial layer of a first conductivity type semiconductor material upon a substrate of semiconductor material having an intrinsic or semi insulating conductivity. Then channels are etched through the epitaxial layer to the semi insulating semiconductor substrate, thereby forming the epitaxial material into a plurality of parallel ribs or ridges. After coating the entire surface of the channels and the ridges with a dielectric layer, a conductive material is deposited over the substrate to fill the channels with the conductive material which may be either a metal or polycrystalline silicon doped to have sufficient conductivity. The surface of the substrate is then lapped to remove the conductive material and the dielectric material from the ridges to expose the first semiconductor material, and following diffusion of a dopant to convert the first semiconductor material to a second conductivity type material thereby forming a PN junction in each of the ridges in spaced locations therealong, suitable metallization is placed on the substrate to connect the first conductivity material to the conductive material in the channels to form column lines and metallization is placed on top a dielectric layer to connect the other conductivity material in a plurality of row lines.

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