| Patent Number |
Title Of Patent |
Date Issued |
| 5963826 |
Method of forming contact hole and multilayered lines structure |
Oct. 5, 1999 |
| 5963825 |
Method of fabrication of semiconductor fuse with polysilicon plate |
Oct. 5, 1999 |
| 5963824 |
Method of making a semiconductor device with adjustable threshold voltage |
Oct. 5, 1999 |
| 5963823 |
Manufacturing method of thin film semiconductor device |
Oct. 5, 1999 |
| 5963822 |
Method of forming selective epitaxial film |
Oct. 5, 1999 |
| 5963821 |
Method of making semiconductor wafers |
Oct. 5, 1999 |
| 5963820 |
Method for forming field oxide or other insulators during the formation of a semiconductor devic... |
Oct. 5, 1999 |
| 5963819 |
Method of fabricating shallow trench isolation |
Oct. 5, 1999 |
| 5963818 |
Combined trench isolation and inlaid process for integrated circuit formation |
Oct. 5, 1999 |
| 5963817 |
Bulk and strained silicon on insulator using local selective oxidation |
Oct. 5, 1999 |
| 5963816 |
Method for making shallow trench marks |
Oct. 5, 1999 |
| 5963815 |
Method for forming a surface-roughened conductive film on a semiconductor wafer |
Oct. 5, 1999 |
| 5963814 |
Method of forming recessed container cells by wet etching conductive layer and dissimilar layer ... |
Oct. 5, 1999 |
| 5963813 |
Integrated circuitry and method of forming a field effect transistor |
Oct. 5, 1999 |
| 5963812 |
Manufacturing method of a semiconductor apparatus having an electron donative surface in a side ... |
Oct. 5, 1999 |
| 5963811 |
Method of fabricating a MOS device with a localized punchthrough stopper |
Oct. 5, 1999 |
| 5963810 |
Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabric... |
Oct. 5, 1999 |
| 5963809 |
Asymmetrical MOSFET with gate pattern after source/drain formation |
Oct. 5, 1999 |
| 5963808 |
Method of forming an asymmetric bird's beak cell for a flash EEPROM |
Oct. 5, 1999 |
| 5963807 |
Silicon carbide field effect transistor with increased avalanche withstand capability |
Oct. 5, 1999 |
| 5963806 |
Method of forming memory cell with built-in erasure feature |
Oct. 5, 1999 |
| 5963805 |
Method for forming integrated circuit capacitors including dual layer electrodes |
Oct. 5, 1999 |
| 5963804 |
Method of making a doped silicon structure with impression image on opposing roughened surfaces |
Oct. 5, 1999 |
| 5963803 |
Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer width... |
Oct. 5, 1999 |
| 5963802 |
CMOS process for forming planarized twin wells |
Oct. 5, 1999 |
| 5963801 |
Method of forming retrograde well structures and punch-through barriers using low energy implant... |
Oct. 5, 1999 |
| 5963800 |
CMOS integration process having vertical channel |
Oct. 5, 1999 |
| 5963799 |
Blanket well counter doping process for high speed/low power MOSFETs |
Oct. 5, 1999 |
| 5963798 |
Fabrication method of CMOS device having buried implanted layers for lateral isolation (BILLI) |
Oct. 5, 1999 |
| 5963797 |
Method of manufacturing semiconductor devices |
Oct. 5, 1999 |
| 5963796 |
Fabrication method for semiconductor package substrate and semiconductor package |
Oct. 5, 1999 |
| 5963795 |
Method of assembling a heat sink assembly |
Oct. 5, 1999 |
| 5963794 |
Angularly offset stacked die multichip device and method of manufacture |
Oct. 5, 1999 |
| 5963793 |
Microelectronic packaging using arched solder columns |
Oct. 5, 1999 |
| 5963792 |
Use of an oxide surface to facilitate gate break on a carrier substrate for a semiconductor devi... |
Oct. 5, 1999 |
| 5963791 |
Silicon carbide MOSFET having self-aligned gate structure and method of fabrication |
Oct. 5, 1999 |
| 5963790 |
Method of producing thin film solar cell |
Oct. 5, 1999 |
| 5963789 |
Method for silicon island formation |
Oct. 5, 1999 |
| 5963788 |
Method for integrating microelectromechanical devices with electronic circuitry |
Oct. 5, 1999 |
| 5963787 |
Method of producing gallium nitride semiconductor light emitting device |
Oct. 5, 1999 |
| 5963786 |
Method of making semiconductor laser with inverted mesa shaped ridge with cervical surface |
Oct. 5, 1999 |
| 5963785 |
Dielectrically-isolated integrated circuit |
Oct. 5, 1999 |
| 5963784 |
Methods of determining parameters of a semiconductor device and the width of an insulative space... |
Oct. 5, 1999 |
| 5963783 |
In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers |
Oct. 5, 1999 |
| 5963782 |
Semiconductor component and method of manufacture |
Oct. 5, 1999 |
| 5963781 |
Technique for determining semiconductor substrate thickness |
Oct. 5, 1999 |
| 5963780 |
Method for detecting defect sizes in polysilicon and source-drain semiconductor devices |
Oct. 5, 1999 |
| 5963779 |
Integrated circuit using a back gate voltage for burn-in operations |
Oct. 5, 1999 |
| 5963778 |
Method for producing near net shape planar sputtering targets and an intermediate therefor |
Oct. 5, 1999 |
| 5963777 |
Hypereutectoid and hypoeutectic binary uranium-vanadium alloys |
Oct. 5, 1999 |
