| Patent Number |
Title Of Patent |
Date Issued |
| 5649185 |
Method and means for providing access to a library of digitized documents and images |
Jul. 15, 1997 |
| 5649184 |
Symmetric/asymmetric shared processing operation in a tightly coupled multiprocessor |
Jul. 15, 1997 |
| 5649183 |
Method for compressing full text indexes with document identifiers and location offsets |
Jul. 15, 1997 |
| 5649182 |
Apparatus and method for organizing timeline data |
Jul. 15, 1997 |
| 5649181 |
Method and apparatus for indexing database columns with bit vectors |
Jul. 15, 1997 |
| 5649180 |
Method for generating hierarchical specification information from software |
Jul. 15, 1997 |
| 5649179 |
Dynamic instruction allocation for a SIMD processor |
Jul. 15, 1997 |
| 5649178 |
Apparatus and method for storing and initializing branch prediction with selective information t... |
Jul. 15, 1997 |
| 5649177 |
Control logic for very fast clock speeds |
Jul. 15, 1997 |
| 5649176 |
Transition analysis and circuit resynthesis method and device for digital circuit modeling |
Jul. 15, 1997 |
| 5649175 |
Method and apparatus for acquiring bus transaction address and command information with no more ... |
Jul. 15, 1997 |
| 5649174 |
Microprocessor with instruction-cycle versus clock-frequency mode selection |
Jul. 15, 1997 |
| 5649173 |
Hardware architecture for image generation and manipulation |
Jul. 15, 1997 |
| 5649172 |
Color mixing device using a high speed image register |
Jul. 15, 1997 |
| 5649171 |
On-line video editing system |
Jul. 15, 1997 |
| 5649170 |
Interconnect and driver optimization for high performance processors |
Jul. 15, 1997 |
| 5649169 |
Method and system for declustering semiconductor defect data |
Jul. 15, 1997 |
| 5649168 |
Computer program product for a query pass through in a heterogeneous distributed data base envir... |
Jul. 15, 1997 |
| 5649167 |
Methods for controlling timing in a logic emulation system |
Jul. 15, 1997 |
| 5649166 |
Dominator selection method for reducing power consumption in a circuit |
Jul. 15, 1997 |
| 5649165 |
Topology-based computer-aided design system for digital circuits and method thereof |
Jul. 15, 1997 |
| 5649164 |
Sets and holds in virtual time logic simulation for parallel processors |
Jul. 15, 1997 |
| 5649163 |
Method of programming an asynchronous load storage device using a representation of a clear/pres... |
Jul. 15, 1997 |
| 5649162 |
Local bus interface |
Jul. 15, 1997 |
| 5649161 |
Prepaging during PCI master initiated wait cycles |
Jul. 15, 1997 |
| 5649160 |
Noise reduction in integrated circuits and circuit assemblies |
Jul. 15, 1997 |
| 5649159 |
Data processor with a multi-level protection mechanism, multi-level protection circuit, and meth... |
Jul. 15, 1997 |
| 5649158 |
Method for incrementally archiving primary storage to archive storage by utilizing both a partit... |
Jul. 15, 1997 |
| 5649157 |
Memory controller with priority queues |
Jul. 15, 1997 |
| 5649156 |
Cache management system utilizing a cache data replacer responsive to cache stress threshold val... |
Jul. 15, 1997 |
| 5649155 |
Cache memory accessed by continuation requests |
Jul. 15, 1997 |
| 5649154 |
Cache memory system having secondary cache integrated with primary cache for use with VLSI circu... |
Jul. 15, 1997 |
| 5649153 |
Aggressive adaption algorithm for selective record caching |
Jul. 15, 1997 |
| 5649152 |
Method and system for providing a static snapshot of data stored on a mass storage system |
Jul. 15, 1997 |
| 5649151 |
Efficient method and apparatus for access and storage of compressed data |
Jul. 15, 1997 |
| 5649150 |
Scannable last-in-first-out register stack |
Jul. 15, 1997 |
| 5649149 |
Integrated content addressable memory array with processing logical and a host computer interfac... |
Jul. 15, 1997 |
| 5649148 |
Fast digital signal processor interface using data interchanging between two memory banks |
Jul. 15, 1997 |
| 5649147 |
Circuit for designating instruction pointers for use by a processor decoder |
Jul. 15, 1997 |
| 5649146 |
Modulo addressing buffer |
Jul. 15, 1997 |
| 5649145 |
Data processor processing a jump instruction |
Jul. 15, 1997 |
| 5649144 |
Apparatus, systems and methods for improving data cache hit rates |
Jul. 15, 1997 |
| 5649143 |
Apparatus and method for providing a cache indexing scheme less susceptible to cache collisions |
Jul. 15, 1997 |
| 5649142 |
Method and apparatus for translating addresses using mask and replacement value registers and fo... |
Jul. 15, 1997 |
| 5649141 |
Multiprocessor system for locally managing address translation table |
Jul. 15, 1997 |
| 5649140 |
System for use in translating virtual addresses into absolute addresses |
Jul. 15, 1997 |
| 5649139 |
Method and apparatus for virtual memory mapping and transaction management in an object-oriented... |
Jul. 15, 1997 |
| 5649138 |
Time dependent rerouting of instructions in plurality of reservation stations of a superscalar m... |
Jul. 15, 1997 |
| 5649137 |
Method and apparatus for store-into-instruction-stream detection and maintaining branch predicti... |
Jul. 15, 1997 |
| 5649136 |
Processor structure and method for maintaining and restoring precise state at any instruction bo... |
Jul. 15, 1997 |
