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Class Information
Number: 717/160
Name: Data processing: software development, installation, and management > Software program development tool (e.g., integrated case tool or stand-alone development tool) > Translation of code > Compiling code > Optimization > Code restructuring > Including loop
Description: Subject matter wherein a code portion to be restructured comprises at least one construct representing a set of repeatedly executing instructions.










Sub-classes under this class:

Class Number Class Name Patents
717/161 Including scheduling instructions 232


Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
8713549 Vectorization of program code Apr. 29, 2014
8694971 Scalable property-sensitive points-to analysis for program code Apr. 8, 2014
8677330 Processors and compiling methods for processors Mar. 18, 2014
8677337 Static profitability control for speculative automatic parallelization Mar. 18, 2014
8677338 Data dependence testing for loop fusion with code replication, array contraction, and loop interchange Mar. 18, 2014
8671401 Tiling across loop nests with possible recomputation Mar. 11, 2014
8640112 Vectorizing combinations of program operations Jan. 28, 2014
8635606 Dynamic optimization using a resource cost registry Jan. 21, 2014
8627300 Parallel dynamic optimization Jan. 7, 2014
8627304 Vectorization of program code Jan. 7, 2014
8601454 Device and method for automatically optimizing composite applications having orchestrated activities Dec. 3, 2013
8601459 Control structure refinement of loops using static analysis Dec. 3, 2013
8589901 Speculative region-level loop optimizations Nov. 19, 2013
8578358 Macroscalar processor architecture Nov. 5, 2013
8555030 Creating multiple versions for interior pointers and alignment of an array Oct. 8, 2013
8555267 Performing register allocation of program variables based on priority spills and assignments Oct. 8, 2013
8549501 Framework for generating mixed-mode operations in loop-level simdization Oct. 1, 2013
8549507 Loop coalescing method and loop coalescing device Oct. 1, 2013
8549508 Mechanism for performing instruction scheduling based on register pressure sensitivity Oct. 1, 2013
8543993 Compiler, compile method, and processor core control method and processor Sep. 24, 2013
8522226 Control structure refinement of loops using static analysis Aug. 27, 2013
8516468 Multiversioning if statement merging and loop fusion Aug. 20, 2013
8505002 Translation of SIMD instructions in a data processing system Aug. 6, 2013
8495606 Redundant exception handling code removal Jul. 23, 2013
8495607 Performing aggressive code optimization with an ability to rollback changes made by the aggressive optimizations Jul. 23, 2013
8484623 Efficient program instrumentation Jul. 9, 2013
8479185 Method and system for utilizing parallelism across loops Jul. 2, 2013
8479179 Compiling method, compiling apparatus and computer system for a loop in a program Jul. 2, 2013
8473931 Method, system and program product for optimizing emulation of a suspected malware Jun. 25, 2013
8468508 Parallelization of irregular reductions via parallel building and exploitation of conflict-free units of work at runtime Jun. 18, 2013
8458682 Conversion of a class oriented data flow program to a structure oriented data flow program with dynamic interpretation of data types Jun. 4, 2013
8458685 Vector atomic memory operation vector update system and method Jun. 4, 2013
8453156 Method and system to perform load balancing of a task-based multi-threaded application May. 28, 2013
8453135 Computation reuse for loops with irregular accesses May. 28, 2013
8453134 Improving data locality and parallelism by code replication May. 28, 2013
8443344 Methods for identifying gating opportunities from a high-level language program and generating a hardware definition May. 14, 2013
8443351 Parallel loops in a workflow May. 14, 2013
8434076 Efficient compilation and execution of imperative-query languages Apr. 30, 2013
8429625 Digital data processing method and system Apr. 23, 2013
8418156 Two-stage commit (TSC) region for dynamic binary optimization in X86 Apr. 9, 2013
8413127 Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations Apr. 2, 2013
8412914 Macroscalar processor architecture Apr. 2, 2013
8402447 Parallelizing sequential frameworks using transactions Mar. 19, 2013
8402450 Map transformation in data parallel code Mar. 19, 2013
8387036 Method and system for execution profiling using loop count variance Feb. 26, 2013
8375375 Auto parallelization of zero-trip loops through the induction variable substitution Feb. 12, 2013
8359587 Runtime profitability control for speculative automatic parallelization Jan. 22, 2013
8327345 Computation table for block computation Dec. 4, 2012
8327344 Array reference safety analysis in the presence of loops with conditional control flow Dec. 4, 2012
8319774 Constant buffering for a computational core of a programmable graphics processing unit Nov. 27, 2012

1 2 3 4 5 6










 
 
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