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Class Information
Number: 716/9
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Floorplanning > Detailed placement (i.e., iterative improvement)
Description: Subject matter comprising means or steps for refining the position assignment, the size or the shape of the circuit block units or cells, and evaluating repeatedly the position assignment of the block units or cells until all the cells are replaced as efficiently as possible in a refined portion of the floor planned layout of a PCB or an LSI.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620922 |
Method and system for optimized circuit autorouting |
Nov. 17, 2009 |
| 7617465 |
Method and mechanism for performing latch-up check on an IC design |
Nov. 10, 2009 |
| 7617467 |
Electrostatic discharge device verification in an integrated circuit |
Nov. 10, 2009 |
| 7614024 |
Method to implement metal fill during integrated circuit design and layout |
Nov. 3, 2009 |
| 7614025 |
Method of placement for iterative implementation flows |
Nov. 3, 2009 |
| 7614028 |
Representation, configuration, and reconfiguration of routing method and system |
Nov. 3, 2009 |
| 7610568 |
Methods and apparatus for making placement sensitive logic modifications |
Oct. 27, 2009 |
| 7607112 |
Method and apparatus for performing metalization in an integrated circuit process |
Oct. 20, 2009 |
| 7607113 |
Wiring pattern determination method and computer program product thereof |
Oct. 20, 2009 |
| 7603640 |
Multilevel IC floorplanner |
Oct. 13, 2009 |
| 7603643 |
Method and system for conducting design explorations of an integrated circuit |
Oct. 13, 2009 |
| 7596773 |
Automating optimal placement of macro-blocks in the design of an integrated circuit |
Sep. 29, 2009 |
| 7594212 |
Automatic pin placement for integrated circuits to aid circuit board design |
Sep. 22, 2009 |
| 7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus |
Sep. 22, 2009 |
| 7594205 |
Interface configurable for use with target/initiator signals |
Sep. 22, 2009 |
| 7590962 |
Design method and architecture for power gate switch placement |
Sep. 15, 2009 |
| 7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid |
Sep. 15, 2009 |
| 7590960 |
Placing partitioned circuit designs within iterative implementation flows |
Sep. 15, 2009 |
| 7587699 |
Automated system for designing and developing field programmable gate arrays |
Sep. 8, 2009 |
| 7587696 |
Semiconductor device, layout method and apparatus and program |
Sep. 8, 2009 |
| 7587695 |
Protection boundaries in a parallel printed circuit board design environment |
Sep. 8, 2009 |
| 7584445 |
Sequence-pair creating apparatus and sequence-pair creating method |
Sep. 1, 2009 |
| 7581198 |
Method and system for the modular design and layout of integrated circuits |
Aug. 25, 2009 |
| 7581201 |
System and method for sign-off timing closure of a VLSI chip |
Aug. 25, 2009 |
| 7577933 |
Timing driven pin assignment |
Aug. 18, 2009 |
| 7571415 |
Layout of power device |
Aug. 4, 2009 |
| 7571410 |
Resonant tree driven clock distribution grid |
Aug. 4, 2009 |
| 7571409 |
Circuit design device and circuit design program |
Aug. 4, 2009 |
| 7571408 |
Methods and apparatus for diagonal route shielding |
Aug. 4, 2009 |
| 7568177 |
System and method for power gating of an integrated circuit |
Jul. 28, 2009 |
| 7565637 |
Method of designing package for semiconductor device, layout design tool for performing the same, and method of manufacturing semiconductor device using the same |
Jul. 21, 2009 |
| 7565638 |
Density-based layer filler for integrated circuit design |
Jul. 21, 2009 |
| RE40855 |
Integrated circuit having a reduced spacing between a bus and adjacent circuitry |
Jul. 14, 2009 |
| 7562327 |
Mask layout design improvement in gate width direction |
Jul. 14, 2009 |
| 7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a substrate |
Jul. 14, 2009 |
| 7555734 |
Processing constraints in computer-aided design for integrated circuits |
Jun. 30, 2009 |
| 7539964 |
Cell placement taking into account consumed current amount |
May. 26, 2009 |
| 7539966 |
Enhanced OP3 algorithms for net cuts, net joins, and probe points for a digital design |
May. 26, 2009 |
| 7536658 |
Power pad synthesizer for an integrated circuit design |
May. 19, 2009 |
| 7536659 |
Semiconductor memory device and semiconductor device |
May. 19, 2009 |
| 7536661 |
Incremental placement during physical synthesis |
May. 19, 2009 |
| 7536664 |
Physical design system and method |
May. 19, 2009 |
| 7536666 |
Integrated circuit and method of routing a clock signal in an integrated circuit |
May. 19, 2009 |
| 7533363 |
System for integrated circuit layout partition and extraction for independent layout processing |
May. 12, 2009 |
| 7533358 |
Integrated sizing, layout, and extractor tool for circuit design |
May. 12, 2009 |
| 7523429 |
System for designing integrated circuits with enhanced manufacturability |
Apr. 21, 2009 |
| 7523430 |
Programmable logic device design tool with simultaneous switching noise awareness |
Apr. 21, 2009 |
| 7523419 |
Semiconductor integrated device for preventing breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof, design method thereof, designing apparatus met |
Apr. 21, 2009 |
| 7519927 |
Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations |
Apr. 14, 2009 |
| 7519933 |
Converging repeater methodology for channel-limited SOC microprocessors |
Apr. 14, 2009 |
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