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Class Information
Number: 716/8
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Floorplanning
Description: Subject matter comprising means or steps for enabling exact judgment of accommodation feasibility of using circuit block units or cells on a layout area of an LSI or PCB at the initial designing stage.

Sub-classes under this class:

Class Number Class Name Patents
716/10 Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance) 1,277
716/9 Detailed placement (i.e., iterative improvement) 775
716/11 Layout editor (e.g., updating) 1,167

Patents under this class:

Patent Number Title Of Patent Date Issued
7805693 IC chip design modeling using perimeter density to electrical characteristic correlation Sep. 28, 2010
7805689 Circuit board information acquisition and conversion method, program, and device for the same Sep. 28, 2010
7802221 Design tool with graphical interconnect matrix Sep. 21, 2010
7802219 Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout Sep. 21, 2010
7797661 Method and apparatus for describing and managing properties of a transformer coil Sep. 14, 2010
7797652 Implementing integrated circuit yield estimation using voronoi diagrams Sep. 14, 2010
7797651 Verifying design isolation using bitstreams Sep. 14, 2010
7788624 Methods of balancing logic resource usage in a programmable logic device Aug. 31, 2010
7788619 Memories, memory compiling systems and methods for the same Aug. 31, 2010
7788612 System, method, and computer program product for matching cell layout of an integrated circuit design Aug. 31, 2010
7785946 Integrated circuits and methods of design and manufacture thereof Aug. 31, 2010
7784011 Reflecting pin swap of PLD performed in package design in circuit design and PLD design Aug. 24, 2010
RE41548 FPGA with hybrid interconnect Aug. 17, 2010
7774733 Method and apparatus for user interface in home network and electronic device and storage medium therefor Aug. 10, 2010
7774732 Method for radiation tolerance by automated placement Aug. 10, 2010
7770080 Using neighborhood functions to extract logical models of physical failures using layout based diagnosis Aug. 3, 2010
7765510 Method of searching for wiring route including vias in integrated circuit Jul. 27, 2010
7765508 Method and system for generating multiple implementation views of an IC design Jul. 27, 2010
7765505 Design rule management method, design rule management program, rule management apparatus and rule verification apparatus Jul. 27, 2010
7761835 Semiconductor device design method, semiconductor device design system, and computer program for extracting parasitic parameters Jul. 20, 2010
7761834 Interactive schematic for use in analog, mixed-signal, and custom digital circuit design Jul. 20, 2010
7761824 System and method to generate an IC layout using simplified manufacturing rule Jul. 20, 2010
7761821 Technology migration for integrated circuits with radical design restrictions Jul. 20, 2010
7761819 System and method of modification of integrated circuit mask layout Jul. 20, 2010
7757193 Structure cluster and method in programmable logic circuit Jul. 13, 2010
7752592 Scheduler design to optimize system performance using configurable acceleration engines Jul. 6, 2010
7752591 Board layout check apparatus and board layout check method for guard wiring Jul. 6, 2010
7752589 Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design Jul. 6, 2010
7752588 Timing driven force directed placement flow Jul. 6, 2010
7752586 Design structure of an integration circuit and test method of the integrated circuit Jul. 6, 2010
7752584 Method for verifying mask pattern of semiconductor device Jul. 6, 2010
7752578 Automatic voltage drop optimization Jul. 6, 2010
7739646 Analog and mixed signal IC layout system Jun. 15, 2010
7739638 Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have Jun. 15, 2010
7739636 Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise Jun. 15, 2010
7738985 Production condition determining method, production condition determining apparatus, mounter, and program Jun. 15, 2010
7737770 Power switches having positive-channel high dielectric constant insulated gate field effect transistors Jun. 15, 2010
7737472 Semiconductor integrated circuit device Jun. 15, 2010
7735040 Method for designing cell layout of a semiconductor integrated circuit with logic having a data flow Jun. 8, 2010
7735036 System and method enabling circuit topology recognition with auto-interactive constraint application and smart checking Jun. 8, 2010
7730442 Apparatus for designing circuit and method for designing circuit according to clearance required between wirings therein Jun. 1, 2010
7730439 Floor plan evaluating method, floor plan correcting method, program, floor plan evaluating device, and floor plan creating device Jun. 1, 2010
7730431 Design method, design apparatus, and computer program for semiconductor integrated circuit Jun. 1, 2010
7725858 Providing a moat capacitance May. 25, 2010
7725857 Method for optimizing organizational floor layout and operations May. 25, 2010
7721248 Circuit element function matching despite auto-generated dummy shapes May. 18, 2010
7721239 Semiconductor integrated circuit with connecting lines for connecting conductive lines of a memory cell array to a driver May. 18, 2010
7721238 Method and apparatus for configurable printed circuit board circuit layout pattern May. 18, 2010
7721171 Scheme to optimize scan chain ordering in designs May. 18, 2010
7716614 Hierarchical feature extraction for electrical interaction calculations May. 11, 2010

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