| |
 |
|
Class Information
Number: 716/8
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Floorplanning
Description: Subject matter comprising means or steps for enabling exact judgment of accommodation feasibility of using circuit block units or cells on a layout area of an LSI or PCB at the initial designing stage.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7617467 |
Electrostatic discharge device verification in an integrated circuit |
Nov. 10, 2009 |
| 7617465 |
Method and mechanism for performing latch-up check on an IC design |
Nov. 10, 2009 |
| 7614025 |
Method of placement for iterative implementation flows |
Nov. 3, 2009 |
| 7614024 |
Method to implement metal fill during integrated circuit design and layout |
Nov. 3, 2009 |
| 7607112 |
Method and apparatus for performing metalization in an integrated circuit process |
Oct. 20, 2009 |
| 7603643 |
Method and system for conducting design explorations of an integrated circuit |
Oct. 13, 2009 |
| 7603641 |
Power/ground wire routing correction and optimization |
Oct. 13, 2009 |
| 7603640 |
Multilevel IC floorplanner |
Oct. 13, 2009 |
| 7603637 |
Secure, stable on chip silicon identification |
Oct. 13, 2009 |
| 7596774 |
Hard macro with configurable side input/output terminals, for a subsystem |
Sep. 29, 2009 |
| 7594206 |
Fault detecting method and layout method for semiconductor integrated circuit |
Sep. 22, 2009 |
| 7594205 |
Interface configurable for use with target/initiator signals |
Sep. 22, 2009 |
| 7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus |
Sep. 22, 2009 |
| 7590962 |
Design method and architecture for power gate switch placement |
Sep. 15, 2009 |
| 7590960 |
Placing partitioned circuit designs within iterative implementation flows |
Sep. 15, 2009 |
| 7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid |
Sep. 15, 2009 |
| 7587695 |
Protection boundaries in a parallel printed circuit board design environment |
Sep. 8, 2009 |
| 7581202 |
Method for generation, placement, and routing of test structures in test chips |
Aug. 25, 2009 |
| 7581198 |
Method and system for the modular design and layout of integrated circuits |
Aug. 25, 2009 |
| 7577931 |
Semiconductor device and method of manufacturing the same |
Aug. 18, 2009 |
| 7571410 |
Resonant tree driven clock distribution grid |
Aug. 4, 2009 |
| 7571408 |
Methods and apparatus for diagonal route shielding |
Aug. 4, 2009 |
| 7568176 |
Method, system, and computer program product for hierarchical integrated circuit repartitioning |
Jul. 28, 2009 |
| 7565637 |
Method of designing package for semiconductor device, layout design tool for performing the same, and method of manufacturing semiconductor device using the same |
Jul. 21, 2009 |
| RE40855 |
Integrated circuit having a reduced spacing between a bus and adjacent circuitry |
Jul. 14, 2009 |
| 7562327 |
Mask layout design improvement in gate width direction |
Jul. 14, 2009 |
| 7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a substrate |
Jul. 14, 2009 |
| 7562316 |
Apparatus for power consumption reduction |
Jul. 14, 2009 |
| 7555733 |
Hierarchical partitioning |
Jun. 30, 2009 |
| 7546559 |
Method of optimization of clock gating in integrated circuit designs |
Jun. 9, 2009 |
| 7543259 |
Method and device for deciding support portion position in a backup device |
Jun. 2, 2009 |
| 7543249 |
Embedded switchable power ring |
Jun. 2, 2009 |
| 7539964 |
Cell placement taking into account consumed current amount |
May. 26, 2009 |
| 7539962 |
Pattern data correcting method, photo mask manufacturing method, semiconductor device manufacturing method, program and semiconductor device |
May. 26, 2009 |
| 7539961 |
Library-based solver for modeling an integrated circuit |
May. 26, 2009 |
| 7539893 |
Systems and methods for speed binning of integrated circuits |
May. 26, 2009 |
| 7536661 |
Incremental placement during physical synthesis |
May. 19, 2009 |
| 7536658 |
Power pad synthesizer for an integrated circuit design |
May. 19, 2009 |
| 7533363 |
System for integrated circuit layout partition and extraction for independent layout processing |
May. 12, 2009 |
| 7533357 |
Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis |
May. 12, 2009 |
| 7530045 |
Recursive partitioning based placement for programmable logic devices using non-rectilinear device-cutlines |
May. 5, 2009 |
| 7526739 |
Methods and systems for computer aided design of 3D integrated circuits |
Apr. 28, 2009 |
| 7524685 |
Manufacturing method of a display device |
Apr. 28, 2009 |
| 7523419 |
Semiconductor integrated device for preventing breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof, design method thereof, designing apparatus met |
Apr. 21, 2009 |
| 7516434 |
Layout design program, layout design device and layout design method for semiconductor integrated circuit |
Apr. 7, 2009 |
| 7512921 |
Method and apparatus for designing integrated circuit enabling the yield of integrated circuit to be improved by considering random errors |
Mar. 31, 2009 |
| 7509622 |
Dummy filling technique for improved planarization of chip surface topography |
Mar. 24, 2009 |
| 7509547 |
System and method for testing of interconnects in a programmable logic device |
Mar. 24, 2009 |
| 7509247 |
Electromagnetic solutions for full-chip analysis |
Mar. 24, 2009 |
| 7502721 |
Product design support system, product design support method, and program |
Mar. 10, 2009 |
|
|
|
