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Class Information
Number: 716/7
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Partitioning (e.g., function block, ordering constraint)
Description: Subject matter comprising means or steps for dividing the circuit design into a set of smaller subcircuits arranged in a logical hierarchical structure.










Patents under this class:
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Patent Number Title Of Patent Date Issued
7805697 Rotary clock synchronous fabric Sep. 28, 2010
7797654 Power network analyzer for an integrated circuit design Sep. 14, 2010
7797659 Analog/digital partitioning of circuit designs for simulation Sep. 14, 2010
7793243 Multi-engine static analysis Sep. 7, 2010
7793241 Power network analyzer for an integrated circuit design Sep. 7, 2010
7788618 Scalable dependent state element identification Aug. 31, 2010
7765498 Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist Jul. 27, 2010
7761828 Partitioning electronic circuit designs into simulation-ready blocks Jul. 20, 2010
7761818 Obtaining a feasible integer solution in a hierarchical circuit layout optimization Jul. 20, 2010
7757188 Method and apparatus for designing integrated circuit Jul. 13, 2010
7757196 Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards Jul. 13, 2010
7752578 Automatic voltage drop optimization Jul. 6, 2010
7739629 Method and mechanism for implementing electronic designs having power information specifications background Jun. 15, 2010
7735036 System and method enabling circuit topology recognition with auto-interactive constraint application and smart checking Jun. 8, 2010
7730438 Methods and apparatuses for designing multiplexers Jun. 1, 2010
7730431 Design method, design apparatus, and computer program for semiconductor integrated circuit Jun. 1, 2010
7725856 Method and apparatus for performing parallel slack computation May. 25, 2010
7725865 Method, storage media storing program, and component for avoiding increase in delay time in semiconductor circuit having plural wiring layers May. 25, 2010
7725850 Methods for design rule checking with abstracted via obstructions May. 25, 2010
7721234 Simulation method and simulation program May. 18, 2010
7721171 Scheme to optimize scan chain ordering in designs May. 18, 2010
7716620 Moment-based method and system for evaluation of metal layer transient currents in an integrated circuit May. 11, 2010
7715995 Design structure for measurement of power consumption within an integrated circuit May. 11, 2010
7712055 Designing integrated circuits for yield May. 4, 2010
7711534 Method and system of design verification May. 4, 2010
7712059 Coverage metric and coverage computation for verification based on design partitions May. 4, 2010
7707532 Techniques for grouping circuit elements into logic blocks Apr. 27, 2010
7707535 Stitched IC chip layout design structure Apr. 27, 2010
7707523 Method of fabricating a semiconductor device and a method of generating a mask pattern Apr. 27, 2010
7703061 IC design modeling allowing dimension-dependent rule checking Apr. 20, 2010
7703060 Stitched IC layout methods, systems and program product Apr. 20, 2010
7703059 Method and apparatus for automatic creation and placement of a floor-plan region Apr. 20, 2010
7698675 Method and design system for semiconductor integrated circuit with a reduced placement area Apr. 13, 2010
7698674 System and method for efficient analysis of point-to-point delay constraints in static timing Apr. 13, 2010
7698679 Method and apparatus for automatic routing yield optimization Apr. 13, 2010
7694256 Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas Apr. 6, 2010
7689958 Partitioning for a massively parallel simulation system Mar. 30, 2010
7689959 Code generator for finite state machines Mar. 30, 2010
7685553 System and method for global circuit routing incorporating estimation of critical area estimate metrics Mar. 23, 2010
7685544 Testing pattern sensitive algorithms for semiconductor design Mar. 23, 2010
7681162 Standard cell, cell library using a standard cell and method for arranging via contact Mar. 16, 2010
7676773 Trace optimization in flattened netlist by storing and retrieving intermediate results Mar. 9, 2010
7673264 System and method for verifying IP integrity in system-on-chip (SOC) design Mar. 2, 2010
7673263 Method for verifying and representing hardware by decomposition and partitioning Mar. 2, 2010
7669174 Pattern generation method and charged particle beam writing apparatus Feb. 23, 2010
7669157 Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Feb. 23, 2010
7669151 Methods for reducing power supply simultaneous switching noise Feb. 23, 2010
7665054 Optimizing circuit layouts by configuring rooms for placing devices Feb. 16, 2010
7657856 Method and system for parallel processing of IC design layouts Feb. 2, 2010
7657854 Method and system for designing test circuit in a system on chip Feb. 2, 2010

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