| |
 |
|
Class Information
Number: 716/7
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Partitioning (e.g., function block, ordering constraint)
Description: Subject matter comprising means or steps for dividing the circuit design into a set of smaller subcircuits arranged in a logical hierarchical structure.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7623995 |
Method of extracting a semiconductor device compact model |
Nov. 24, 2009 |
| 7624365 |
Semiconductor integrated device and apparatus for designing the same |
Nov. 24, 2009 |
| 7614033 |
Mask data preparation |
Nov. 3, 2009 |
| 7610574 |
Method and apparatus for designing fine pattern |
Oct. 27, 2009 |
| 7607117 |
Representing device layout using tree structure |
Oct. 20, 2009 |
| 7603640 |
Multilevel IC floorplanner |
Oct. 13, 2009 |
| 7600211 |
Toggle equivalence preserving logic synthesis |
Oct. 6, 2009 |
| 7596772 |
Methodology and system for setup/hold time characterization of analog IP |
Sep. 29, 2009 |
| 7594210 |
Timing variation characterization |
Sep. 22, 2009 |
| 7594201 |
Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code |
Sep. 22, 2009 |
| 7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus |
Sep. 22, 2009 |
| 7590960 |
Placing partitioned circuit designs within iterative implementation flows |
Sep. 15, 2009 |
| 7584444 |
System and method for external-memory graph search utilizing edge partitioning |
Sep. 1, 2009 |
| 7581197 |
Relative positioning of circuit elements in circuit design |
Aug. 25, 2009 |
| 7580824 |
Apparatus and methods for modeling power characteristics of electronic circuitry |
Aug. 25, 2009 |
| 7577927 |
IC design modeling allowing dimension-dependent rule checking |
Aug. 18, 2009 |
| 7571403 |
Circuit verification |
Aug. 4, 2009 |
| 7568176 |
Method, system, and computer program product for hierarchical integrated circuit repartitioning |
Jul. 28, 2009 |
| 7568179 |
Layout printability optimization method and system |
Jul. 28, 2009 |
| 7565635 |
SiP (system in package) design systems and methods |
Jul. 21, 2009 |
| 7562316 |
Apparatus for power consumption reduction |
Jul. 14, 2009 |
| 7562325 |
Device to cluster Boolean functions for clock gating |
Jul. 14, 2009 |
| 7555738 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Jun. 30, 2009 |
| 7555733 |
Hierarchical partitioning |
Jun. 30, 2009 |
| 7555734 |
Processing constraints in computer-aided design for integrated circuits |
Jun. 30, 2009 |
| 7546567 |
Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip |
Jun. 9, 2009 |
| 7546560 |
Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist |
Jun. 9, 2009 |
| 7546559 |
Method of optimization of clock gating in integrated circuit designs |
Jun. 9, 2009 |
| 7530035 |
Automatic power grid synthesis method and computer readable recording medium for storing program thereof |
May. 5, 2009 |
| 7530045 |
Recursive partitioning based placement for programmable logic devices using non-rectilinear device-cutlines |
May. 5, 2009 |
| 7526745 |
Method for specification and integration of reusable IP constraints |
Apr. 28, 2009 |
| 7519926 |
Semiconductor device and method for designing the same |
Apr. 14, 2009 |
| 7516433 |
Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit |
Apr. 7, 2009 |
| 7516423 |
Method and apparatus for designing electronic circuits using optimization |
Apr. 7, 2009 |
| 7509247 |
Electromagnetic solutions for full-chip analysis |
Mar. 24, 2009 |
| 7509611 |
Heuristic clustering of circuit elements in a circuit design |
Mar. 24, 2009 |
| 7509595 |
Method and system for enabling energy efficient wireless connectivity |
Mar. 24, 2009 |
| 7506278 |
Method and apparatus for improving multiplexer implementation on integrated circuits |
Mar. 17, 2009 |
| 7506290 |
Method and system for case-splitting on nodes in a symbolic simulation framework |
Mar. 17, 2009 |
| 7496875 |
Designing method for designing electronic component |
Feb. 24, 2009 |
| 7496879 |
Concurrent optimization of physical design and operational cycle assignment |
Feb. 24, 2009 |
| 7493575 |
Method for generating and evaluating a table model for circuit simulation |
Feb. 17, 2009 |
| 7480610 |
Software state replay |
Jan. 20, 2009 |
| 7478027 |
Systems, methods, and media for simulation of integrated hardware and software designs |
Jan. 13, 2009 |
| 7478351 |
Designing system and method for designing a system LSI |
Jan. 13, 2009 |
| 7478352 |
Method for creating box level groupings of components and connections in a dynamic layout system |
Jan. 13, 2009 |
| 7474011 |
Method for improved single event latch up resistance in an integrated circuit |
Jan. 6, 2009 |
| 7475371 |
Method and system for case-splitting on nodes in a symbolic simulation framework |
Jan. 6, 2009 |
| 7472359 |
Behavioral transformations for hardware synthesis and code optimization based on Taylor Expansion Diagrams |
Dec. 30, 2008 |
| 7469401 |
Method for using partitioned masks to build a chip |
Dec. 23, 2008 |
|
|
|
