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Class Information
Number: 716/6
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Testing or evaluating > Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width) > Timing analysis (e.g., delay time, path delay, latch timing)
Description: Subject matter wherein the design verification is confirmed based on timing constraints such as delay or latch timing of the circuit components.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620921 |
IC chip at-functional-speed testing with process coverage evaluation |
Nov. 17, 2009 |
| 7620920 |
Time separated signals |
Nov. 17, 2009 |
| 7620857 |
Controllable delay device |
Nov. 17, 2009 |
| 7617466 |
Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device |
Nov. 10, 2009 |
| 7617465 |
Method and mechanism for performing latch-up check on an IC design |
Nov. 10, 2009 |
| 7614024 |
Method to implement metal fill during integrated circuit design and layout |
Nov. 3, 2009 |
| 7614023 |
System for estimating a terminal capacitance and for characterizing a circuit |
Nov. 3, 2009 |
| 7610567 |
Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs |
Oct. 27, 2009 |
| 7610566 |
Method and apparatus for function decomposition |
Oct. 27, 2009 |
| 7607116 |
Method and apparatus for verifying system-on-chip model |
Oct. 20, 2009 |
| 7607115 |
System, method and computer program product for timing-independent sequential equivalence verification |
Oct. 20, 2009 |
| 7603639 |
Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry |
Oct. 13, 2009 |
| 7600206 |
Method of estimating the signal delay in a VLSI circuit |
Oct. 6, 2009 |
| 7600205 |
Net/wiring selection method, net selection method, wiring selection method, and delay improvement method |
Oct. 6, 2009 |
| 7599826 |
System and method for generating various simulation conditions for simulation analysis |
Oct. 6, 2009 |
| 7596775 |
Method for determining a standard cell for IC design |
Sep. 29, 2009 |
| 7596774 |
Hard macro with configurable side input/output terminals, for a subsystem |
Sep. 29, 2009 |
| 7596772 |
Methodology and system for setup/hold time characterization of analog IP |
Sep. 29, 2009 |
| 7594211 |
Methods and apparatuses for reset conditioning in integrated circuits |
Sep. 22, 2009 |
| 7594210 |
Timing variation characterization |
Sep. 22, 2009 |
| 7594209 |
Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis |
Sep. 22, 2009 |
| 7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage |
Sep. 22, 2009 |
| 7594202 |
Optimization of circuit designs using a continuous spectrum of library cells |
Sep. 22, 2009 |
| 7590964 |
Method and system for automatic generation of processor datapaths using instruction set architecture implementing means |
Sep. 15, 2009 |
| 7590961 |
Integrated circuit with signal skew adjusting cell selected from cell library |
Sep. 15, 2009 |
| 7590958 |
Method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities |
Sep. 15, 2009 |
| 7590957 |
Method and apparatus for fixing best case hold time violations in an integrated circuit design |
Sep. 15, 2009 |
| 7590953 |
Static timing analysis and dynamic simulation for custom and ASIC designs |
Sep. 15, 2009 |
| 7587700 |
Process monitoring system and method for processing a large number of sub-micron measurement targets |
Sep. 8, 2009 |
| 7587699 |
Automated system for designing and developing field programmable gate arrays |
Sep. 8, 2009 |
| 7587696 |
Semiconductor device, layout method and apparatus and program |
Sep. 8, 2009 |
| 7587693 |
Apparatus and method of delay calculation for structured ASIC |
Sep. 8, 2009 |
| 7587691 |
Method and apparatus for facilitating variation-aware parasitic extraction |
Sep. 8, 2009 |
| 7587690 |
Method and system for global coverage analysis |
Sep. 8, 2009 |
| 7587689 |
Method of supporting wiring design, supporting apparatus using the method, and computer-readable recording medium |
Sep. 8, 2009 |
| 7584450 |
Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout |
Sep. 1, 2009 |
| 7584443 |
Clock domain conflict analysis for timing graphs |
Sep. 1, 2009 |
| 7584442 |
Method and apparatus for generating memory models and timing database |
Sep. 1, 2009 |
| 7584441 |
Method for generating optimized constraint systems for retimable digital designs |
Sep. 1, 2009 |
| 7584439 |
Cell modeling for integrated circuit design with characterization of upstream driver strength |
Sep. 1, 2009 |
| 7584438 |
Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array |
Sep. 1, 2009 |
| 7581201 |
System and method for sign-off timing closure of a VLSI chip |
Aug. 25, 2009 |
| 7581199 |
Use of state nodes for efficient simulation of large digital circuits at the transistor level |
Aug. 25, 2009 |
| 7577933 |
Timing driven pin assignment |
Aug. 18, 2009 |
| 7577930 |
Method and apparatus for analyzing integrated circuit operations |
Aug. 18, 2009 |
| 7577928 |
Verification of an extracted timing model file |
Aug. 18, 2009 |
| 7574687 |
Method and system to optimize timing margin in a system in package module |
Aug. 11, 2009 |
| 7574344 |
Static timing based IR drop analysis |
Aug. 11, 2009 |
| 7571414 |
Multi-project system-on-chip and its method |
Aug. 4, 2009 |
| 7571407 |
Semiconductor integrated circuit and method of testing delay thereof |
Aug. 4, 2009 |
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