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Class Information
Number: 716/6
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Testing or evaluating > Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width) > Timing analysis (e.g., delay time, path delay, latch timing)
Description: Subject matter wherein the design verification is confirmed based on timing constraints such as delay or latch timing of the circuit components.

Patents under this class:

Patent Number Title Of Patent Date Issued
7805697 Rotary clock synchronous fabric Sep. 28, 2010
7805693 IC chip design modeling using perimeter density to electrical characteristic correlation Sep. 28, 2010
7802217 Leakage power optimization considering gate input activity and timing slack Sep. 21, 2010
7802216 Area and power saving standard cell methodology Sep. 21, 2010
7802215 System and method for providing an improved sliding window scheme for clock mesh analysis Sep. 21, 2010
7802214 Methods and apparatuses for timing analysis of electronics circuits Sep. 21, 2010
7802213 Method and apparatus for circuit design and retiming Sep. 21, 2010
7802212 Processor controlled interface Sep. 21, 2010
7802209 Method for reducing timing libraries for intra-die model in statistical static timing analysis Sep. 21, 2010
7801718 Analyzing timing uncertainty in mesh-based architectures Sep. 21, 2010
7797677 Using scripts for netlisting in a high-level modeling system Sep. 14, 2010
7797668 Method for optimally converting a circuit design into a semiconductor device Sep. 14, 2010
7797658 Multithreaded static timing analysis Sep. 14, 2010
7797657 Parameter ordering for multi-corner static timing analysis Sep. 14, 2010
7797652 Implementing integrated circuit yield estimation using voronoi diagrams Sep. 14, 2010
7797601 Slack-based transition-fault testing Sep. 14, 2010
7795939 Method and system for setup/hold characterization in sequential cells Sep. 14, 2010
RE41704 Timing signal generation for charge-coupled device Sep. 14, 2010
7793247 Method and apparatus for directed physical implementation of a circuit design for an integrated circuit Sep. 7, 2010
7793245 Statistical iterative timing analysis of circuits having latches and/or feedback loops Sep. 7, 2010
7793244 Timing analysis method and timing analysis apparatus Sep. 7, 2010
7793243 Multi-engine static analysis Sep. 7, 2010
7793239 Method and system of modeling leakage Sep. 7, 2010
7791357 On silicon interconnect capacitance extraction Sep. 7, 2010
7788625 Method and apparatus for precharacterizing systems for use in system level design of integrated circuits Aug. 31, 2010
7788624 Methods of balancing logic resource usage in a programmable logic device Aug. 31, 2010
7788620 Input/output placement systems and methods to reduce simultaneous switching output noise Aug. 31, 2010
7788618 Scalable dependent state element identification Aug. 31, 2010
7788617 Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis Aug. 31, 2010
7788614 Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas Aug. 31, 2010
7788613 Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture Aug. 31, 2010
7784006 Method and apparatus for directed physical implementation of a circuit design for an integrated circuit Aug. 24, 2010
7784003 Estimation of process variation impact of slack in multi-corner path-based static timing analysis Aug. 24, 2010
7783467 Method for digital system modeling by using higher software simulator Aug. 24, 2010
7779380 Data processing apparatus including reconfigurable logic circuit Aug. 17, 2010
7779286 Design tool clock domain crossing management Aug. 17, 2010
7778815 Method for the fast exploration of bus-based communication architectures at the cycle-count-accurate-at-transaction-boundaries (CCATB) abstraction Aug. 17, 2010
7778814 Method and device for simulating an automation system Aug. 17, 2010
7774731 Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis Aug. 10, 2010
7774730 Method of and system for designing semiconductor integrated circuit Aug. 10, 2010
7774729 Method and apparatus for reducing dynamic power in a system Aug. 10, 2010
7774728 Method that allows flexible evaluation of power-gated circuits Aug. 10, 2010
7774725 Computationally efficient modeling and simulation of large scale systems Aug. 10, 2010
7774174 Branch merge reduction of RLCM networks Aug. 10, 2010
7770143 System and method for design development Aug. 3, 2010
7769577 Hardware accelerator with a single partition for latches and combinational logic Aug. 3, 2010
7765513 Configuration database supporting selective presentation of configuration entities Jul. 27, 2010
7765511 Compensation for performance variation in integrated circuits Jul. 27, 2010
7765503 Half cycle common path pessimism removal method Jul. 27, 2010
7761832 Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model Jul. 20, 2010

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