| |
 |
|
Class Information
Number: 716/5
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Testing or evaluating > Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)
Description: Subject matter comprising means or steps for checking and confirming the circuit component s layout for consistency of the functional and logical correctness.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620926 |
Methods and structures for flexible power management in integrated circuits |
Nov. 17, 2009 |
| 7620922 |
Method and system for optimized circuit autorouting |
Nov. 17, 2009 |
| 7620919 |
Method and system for logic equivalence checking |
Nov. 17, 2009 |
| 7617474 |
System and method for providing defect printability analysis of photolithographic masks with job-based automation |
Nov. 10, 2009 |
| 7617469 |
Assertion description conversion device, method and computer program product |
Nov. 10, 2009 |
| 7617468 |
Method for automatic maximization of coverage in constrained stimulus driven simulation |
Nov. 10, 2009 |
| 7617467 |
Electrostatic discharge device verification in an integrated circuit |
Nov. 10, 2009 |
| 7617466 |
Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device |
Nov. 10, 2009 |
| 7617465 |
Method and mechanism for performing latch-up check on an IC design |
Nov. 10, 2009 |
| 7617464 |
Verifying an IC layout in individual regions and combining results |
Nov. 10, 2009 |
| 7617463 |
Power supply method for semiconductor integrated circuit in test and CAD system for semiconductor integrated circuit |
Nov. 10, 2009 |
| 7614024 |
Method to implement metal fill during integrated circuit design and layout |
Nov. 3, 2009 |
| 7614023 |
System for estimating a terminal capacitance and for characterizing a circuit |
Nov. 3, 2009 |
| 7610571 |
Method and system for simulating state retention of an RTL design |
Oct. 27, 2009 |
| 7610570 |
Method and mechanism for using systematic local search for SAT solving |
Oct. 27, 2009 |
| 7610569 |
Chip design verification apparatus and data communication method for the same |
Oct. 27, 2009 |
| 7610568 |
Methods and apparatus for making placement sensitive logic modifications |
Oct. 27, 2009 |
| 7607116 |
Method and apparatus for verifying system-on-chip model |
Oct. 20, 2009 |
| 7607115 |
System, method and computer program product for timing-independent sequential equivalence verification |
Oct. 20, 2009 |
| 7607114 |
Designer's intent tolerance bands for proximity correction and checking |
Oct. 20, 2009 |
| 7603639 |
Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry |
Oct. 13, 2009 |
| 7603636 |
Assertion generating system, program thereof, circuit verifying system, and assertion generating method |
Oct. 13, 2009 |
| 7600211 |
Toggle equivalence preserving logic synthesis |
Oct. 6, 2009 |
| 7600209 |
Generating constraint preserving testcases in the presence of dead-end constraints |
Oct. 6, 2009 |
| 7600208 |
Automatic placement of decoupling capacitors |
Oct. 6, 2009 |
| 7600206 |
Method of estimating the signal delay in a VLSI circuit |
Oct. 6, 2009 |
| 7600202 |
Techniques for providing a failures in time (FIT) rate for a product design process |
Oct. 6, 2009 |
| 7596772 |
Methodology and system for setup/hold time characterization of analog IP |
Sep. 29, 2009 |
| 7596771 |
Distributed element generator, method of generating distributed elements and an electronic design automation tool employing the same |
Sep. 29, 2009 |
| 7596770 |
Temporal decomposition for design and verification |
Sep. 29, 2009 |
| 7594209 |
Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis |
Sep. 22, 2009 |
| 7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage |
Sep. 22, 2009 |
| 7594207 |
Computationally efficient design rule checking for circuit interconnect routing design |
Sep. 22, 2009 |
| 7594202 |
Optimization of circuit designs using a continuous spectrum of library cells |
Sep. 22, 2009 |
| 7590968 |
Methods for risk-informed chip layout generation |
Sep. 15, 2009 |
| 7590957 |
Method and apparatus for fixing best case hold time violations in an integrated circuit design |
Sep. 15, 2009 |
| 7590956 |
Methods of detecting unwanted logic in an operational circuit design |
Sep. 15, 2009 |
| 7590954 |
Test solution development method |
Sep. 15, 2009 |
| 7590953 |
Static timing analysis and dynamic simulation for custom and ASIC designs |
Sep. 15, 2009 |
| 7587700 |
Process monitoring system and method for processing a large number of sub-micron measurement targets |
Sep. 8, 2009 |
| 7587693 |
Apparatus and method of delay calculation for structured ASIC |
Sep. 8, 2009 |
| 7587692 |
Method and apparatus for full-chip thermal analysis of semiconductor chip designs |
Sep. 8, 2009 |
| 7587691 |
Method and apparatus for facilitating variation-aware parasitic extraction |
Sep. 8, 2009 |
| 7587690 |
Method and system for global coverage analysis |
Sep. 8, 2009 |
| 7587688 |
User-directed timing-driven synthesis |
Sep. 8, 2009 |
| 7586201 |
Wiring modeling technique |
Sep. 8, 2009 |
| 7584460 |
Process and apparatus for abstracting IC design files |
Sep. 1, 2009 |
| 7584450 |
Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout |
Sep. 1, 2009 |
| 7584442 |
Method and apparatus for generating memory models and timing database |
Sep. 1, 2009 |
| 7584440 |
Method and system for tuning a circuit |
Sep. 1, 2009 |
|
|
|
