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Class Information
Number: 716/5
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Testing or evaluating > Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)
Description: Subject matter comprising means or steps for checking and confirming the circuit component s layout for consistency of the functional and logical correctness.










Sub-classes under this class:

Class Number Class Name Patents
716/6 Timing analysis (e.g., delay time, path delay, latch timing) 1,929


Patents under this class:

Patent Number Title Of Patent Date Issued
7805698 Methods and systems for physical hierarchy configuration engine and graphical editor Sep. 28, 2010
7805693 IC chip design modeling using perimeter density to electrical characteristic correlation Sep. 28, 2010
7805692 Method for local hot spot fixing Sep. 28, 2010
7805687 One-time programmable (OTP) memory cell Sep. 28, 2010
7802217 Leakage power optimization considering gate input activity and timing slack Sep. 21, 2010
7802215 System and method for providing an improved sliding window scheme for clock mesh analysis Sep. 21, 2010
7802211 Method and device for verifying digital circuits Sep. 21, 2010
7802210 Methods and systems for analyzing layouts of semiconductor integrated circuit devices Sep. 21, 2010
7797677 Using scripts for netlisting in a high-level modeling system Sep. 14, 2010
7797668 Method for optimally converting a circuit design into a semiconductor device Sep. 14, 2010
7797656 Method of checking and correcting mask pattern Sep. 14, 2010
7797655 Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage Sep. 14, 2010
7797654 Power network analyzer for an integrated circuit design Sep. 14, 2010
7797653 Circuit verification apparatus, circuit verification method, and signal distribution method for the same Sep. 14, 2010
7797652 Implementing integrated circuit yield estimation using voronoi diagrams Sep. 14, 2010
7797648 Solving constraint satisfiability problem for automatic generation of design verification vectors Sep. 14, 2010
7795072 Structure and method of high performance two layer ball grid array substrate Sep. 14, 2010
7793245 Statistical iterative timing analysis of circuits having latches and/or feedback loops Sep. 7, 2010
7793243 Multi-engine static analysis Sep. 7, 2010
7793242 Method and system for performing heuristic constraint simplification Sep. 7, 2010
7793241 Power network analyzer for an integrated circuit design Sep. 7, 2010
7793240 Compensating for layout dimension effects in semiconductor device modeling Sep. 7, 2010
7788630 Method and apparatus for determining an optical model that models the effect of optical proximity correction Aug. 31, 2010
7788618 Scalable dependent state element identification Aug. 31, 2010
7788617 Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis Aug. 31, 2010
7788616 Method and system for performing heuristic constraint simplification Aug. 31, 2010
7788615 Computer program product for verification using reachability overapproximation Aug. 31, 2010
7788614 Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas Aug. 31, 2010
7788613 Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture Aug. 31, 2010
7788612 System, method, and computer program product for matching cell layout of an integrated circuit design Aug. 31, 2010
7788610 Random stimuli generation of memory maps and memory allocations Aug. 31, 2010
7788078 Processor/memory co-exploration at multiple abstraction levels Aug. 31, 2010
7788076 Interference analysis method, interference analysis device, interference analysis program and recording medium with interference analysis program recorded thereon Aug. 31, 2010
7784015 Method for generating a mask layout and constructing an integrated circuit Aug. 24, 2010
7784007 Method for automatically producing layout information Aug. 24, 2010
7784002 Systems for using relative positioning in structures with dynamic ranges Aug. 24, 2010
7784001 Circuit design method, circuit design system, and program product for causing computer to perform circuit design Aug. 24, 2010
7783998 Method and system for prototyping electronic devices with multi-configuration CHIP carriers Aug. 24, 2010
7779378 Computer program product for extending incremental verification of circuit design to encompass verification restraints Aug. 17, 2010
7779377 Method and apparatus for aiding verification of circuit, and computer product Aug. 17, 2010
7779376 Operation analysis method of semiconductor integrated circuit Aug. 17, 2010
7779371 Methods, systems and user interface for evaluating product designs in light of promulgated standards Aug. 17, 2010
7774731 Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis Aug. 10, 2010
7774727 Layout making equipment of semiconductor integrated circuit, method of making layout of semiconductor integrated circuit and process of manufacture of semiconductor device Aug. 10, 2010
7774725 Computationally efficient modeling and simulation of large scale systems Aug. 10, 2010
7770142 Modeling power management for an integrated circuit Aug. 3, 2010
7770141 Computer recording medium for storing program of checking design rule of layout Aug. 3, 2010
7769569 Method and system for designing a structural level description of an electronic circuit Aug. 3, 2010
7765518 System and method for implementing optical rule checking to identify and quantify corner rounding errors Jul. 27, 2010
7765514 Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables Jul. 27, 2010











 
 
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