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Class Information
Number: 716/4
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Testing or evaluating
Description: Subject matter comprising means or steps for determining (i.e., evaluating) the performance of the designed circuit components.

Sub-classes under this class:

Class Number Class Name Patents
716/5 Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width) 2,521

Patents under this class:

Patent Number Title Of Patent Date Issued
7805698 Methods and systems for physical hierarchy configuration engine and graphical editor Sep. 28, 2010
7805693 IC chip design modeling using perimeter density to electrical characteristic correlation Sep. 28, 2010
7805692 Method for local hot spot fixing Sep. 28, 2010
7805691 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program Sep. 28, 2010
7805689 Circuit board information acquisition and conversion method, program, and device for the same Sep. 28, 2010
7805687 One-time programmable (OTP) memory cell Sep. 28, 2010
7802229 Timed loop with sequence frames structure for a graphical program Sep. 21, 2010
7802218 Layout analysis method and apparatus for semiconductor integrated circuit Sep. 21, 2010
7802217 Leakage power optimization considering gate input activity and timing slack Sep. 21, 2010
7802216 Area and power saving standard cell methodology Sep. 21, 2010
7802210 Methods and systems for analyzing layouts of semiconductor integrated circuit devices Sep. 21, 2010
7801699 Regression test modules for detecting and reporting changes in process design kits Sep. 21, 2010
7801636 Method and system for managing wafer processing Sep. 21, 2010
7797677 Using scripts for netlisting in a high-level modeling system Sep. 14, 2010
7797668 Method for optimally converting a circuit design into a semiconductor device Sep. 14, 2010
7797664 System for configuring an integrated circuit and method thereof Sep. 14, 2010
7797663 Conductive dome probes for measuring system level multi-GHZ signals Sep. 14, 2010
7797658 Multithreaded static timing analysis Sep. 14, 2010
7797656 Method of checking and correcting mask pattern Sep. 14, 2010
7797653 Circuit verification apparatus, circuit verification method, and signal distribution method for the same Sep. 14, 2010
7797652 Implementing integrated circuit yield estimation using voronoi diagrams Sep. 14, 2010
7797651 Verifying design isolation using bitstreams Sep. 14, 2010
7797650 System and method for testing SLB and TLB cells during processor design verification and validation Sep. 14, 2010
7797649 Method and system for implementing an analytical wirelength formulation Sep. 14, 2010
7797648 Solving constraint satisfiability problem for automatic generation of design verification vectors Sep. 14, 2010
7797123 Method and apparatus for extracting assume properties from a constrained random test-bench Sep. 14, 2010
7797068 Defect probability calculating method and semiconductor device manufacturing method Sep. 14, 2010
RE41704 Timing signal generation for charge-coupled device Sep. 14, 2010
7793245 Statistical iterative timing analysis of circuits having latches and/or feedback loops Sep. 7, 2010
7793243 Multi-engine static analysis Sep. 7, 2010
7793242 Method and system for performing heuristic constraint simplification Sep. 7, 2010
7793240 Compensating for layout dimension effects in semiconductor device modeling Sep. 7, 2010
7793239 Method and system of modeling leakage Sep. 7, 2010
7792663 Circuit simulation method Sep. 7, 2010
7791978 Design structure of implementing power savings during addressing of DRAM architectures Sep. 7, 2010
7788646 Method for optimizing integrated circuit device design and service Aug. 31, 2010
7788630 Method and apparatus for determining an optical model that models the effect of optical proximity correction Aug. 31, 2010
7788618 Scalable dependent state element identification Aug. 31, 2010
7788617 Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis Aug. 31, 2010
7788616 Method and system for performing heuristic constraint simplification Aug. 31, 2010
7788615 Computer program product for verification using reachability overapproximation Aug. 31, 2010
7788612 System, method, and computer program product for matching cell layout of an integrated circuit design Aug. 31, 2010
7788611 Method for modeling large-area transistor devices, and computer program product therefor Aug. 31, 2010
7788610 Random stimuli generation of memory maps and memory allocations Aug. 31, 2010
7788556 System and method for evaluating an erroneous state associated with a target circuit Aug. 31, 2010
7788079 Methods for producing equivalent circuit models of multi-layer circuits and apparatus using the same Aug. 31, 2010
7788078 Processor/memory co-exploration at multiple abstraction levels Aug. 31, 2010
7788076 Interference analysis method, interference analysis device, interference analysis program and recording medium with interference analysis program recorded thereon Aug. 31, 2010
7784015 Method for generating a mask layout and constructing an integrated circuit Aug. 24, 2010
7784004 Skew lots for IC oscillators and other analog circuits Aug. 24, 2010

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