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Class Information
Number: 716/4
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Testing or evaluating
Description: Subject matter comprising means or steps for determining (i.e., evaluating) the performance of the designed circuit components.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620922 |
Method and system for optimized circuit autorouting |
Nov. 17, 2009 |
| 7620920 |
Time separated signals |
Nov. 17, 2009 |
| 7620919 |
Method and system for logic equivalence checking |
Nov. 17, 2009 |
| 7620918 |
Method and system for logic equivalence checking |
Nov. 17, 2009 |
| 7620883 |
Techniques for mitigating, detecting, and correcting single event upset effects |
Nov. 17, 2009 |
| 7620853 |
Methods for detecting resistive bridging faults at configuration random-access memory output nodes |
Nov. 17, 2009 |
| 7620827 |
Methods and apparatus for cooling integrated circuits |
Nov. 17, 2009 |
| 7617477 |
Method for selecting and optimizing exposure tool using an individual mask error model |
Nov. 10, 2009 |
| 7617474 |
System and method for providing defect printability analysis of photolithographic masks with job-based automation |
Nov. 10, 2009 |
| 7617469 |
Assertion description conversion device, method and computer program product |
Nov. 10, 2009 |
| 7617467 |
Electrostatic discharge device verification in an integrated circuit |
Nov. 10, 2009 |
| 7617466 |
Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device |
Nov. 10, 2009 |
| 7617465 |
Method and mechanism for performing latch-up check on an IC design |
Nov. 10, 2009 |
| 7617463 |
Power supply method for semiconductor integrated circuit in test and CAD system for semiconductor integrated circuit |
Nov. 10, 2009 |
| 7617084 |
Mechanism and method for simultaneous processing and debugging of multiple programming languages |
Nov. 10, 2009 |
| 7616805 |
Pattern defect inspection method and apparatus |
Nov. 10, 2009 |
| 7614024 |
Method to implement metal fill during integrated circuit design and layout |
Nov. 3, 2009 |
| 7614022 |
Testing for bridge faults in the interconnect of programmable integrated circuits |
Nov. 3, 2009 |
| 7614021 |
Optimal amplifier performance selection method |
Nov. 3, 2009 |
| 7613968 |
Device and method for JTAG test |
Nov. 3, 2009 |
| 7613599 |
Method and system for virtual prototyping |
Nov. 3, 2009 |
| 7610570 |
Method and mechanism for using systematic local search for SAT solving |
Oct. 27, 2009 |
| 7610569 |
Chip design verification apparatus and data communication method for the same |
Oct. 27, 2009 |
| 7610568 |
Methods and apparatus for making placement sensitive logic modifications |
Oct. 27, 2009 |
| 7607116 |
Method and apparatus for verifying system-on-chip model |
Oct. 20, 2009 |
| 7607057 |
Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip |
Oct. 20, 2009 |
| 7606694 |
Framework for cycle accurate simulation |
Oct. 20, 2009 |
| 7603647 |
Recognition of a state machine in high-level integrated circuit description language code |
Oct. 13, 2009 |
| 7603638 |
Method and system for modeling statistical leakage-current distribution |
Oct. 13, 2009 |
| 7603637 |
Secure, stable on chip silicon identification |
Oct. 13, 2009 |
| 7603636 |
Assertion generating system, program thereof, circuit verifying system, and assertion generating method |
Oct. 13, 2009 |
| 7600212 |
Method of compensating photomask data for the effects of etch and lithography processes |
Oct. 6, 2009 |
| 7600211 |
Toggle equivalence preserving logic synthesis |
Oct. 6, 2009 |
| 7600209 |
Generating constraint preserving testcases in the presence of dead-end constraints |
Oct. 6, 2009 |
| 7600207 |
Stress-managed revision of integrated circuit layouts |
Oct. 6, 2009 |
| 7600206 |
Method of estimating the signal delay in a VLSI circuit |
Oct. 6, 2009 |
| 7600204 |
Method for simulation of negative bias and temperature instability |
Oct. 6, 2009 |
| 7600203 |
Circuit design system and circuit design program |
Oct. 6, 2009 |
| 7600202 |
Techniques for providing a failures in time (FIT) rate for a product design process |
Oct. 6, 2009 |
| 7599826 |
System and method for generating various simulation conditions for simulation analysis |
Oct. 6, 2009 |
| 7599823 |
Automated approach to resolving artificial algebraic loops |
Oct. 6, 2009 |
| 7596776 |
Light intensity distribution simulation method and computer program product |
Sep. 29, 2009 |
| 7596774 |
Hard macro with configurable side input/output terminals, for a subsystem |
Sep. 29, 2009 |
| 7596770 |
Temporal decomposition for design and verification |
Sep. 29, 2009 |
| 7596423 |
Method and apparatus for verifying a site-dependent procedure |
Sep. 29, 2009 |
| 7594213 |
Method and apparatus for computing dummy feature density for chemical-mechanical polishing |
Sep. 22, 2009 |
| 7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage |
Sep. 22, 2009 |
| 7594207 |
Computationally efficient design rule checking for circuit interconnect routing design |
Sep. 22, 2009 |
| 7594206 |
Fault detecting method and layout method for semiconductor integrated circuit |
Sep. 22, 2009 |
| 7594205 |
Interface configurable for use with target/initiator signals |
Sep. 22, 2009 |
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