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Class Information
Number: 716/3
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Translation (e.g., conversion, equivalence)
Description: Subject matter comprising means or steps for converting an original circuit design data to a target circuit design data having different circuit components while performing the same function as the original circuit design by utilizing a rule group for the conversion.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7627838 |
Automated integrated circuit development |
Dec. 1, 2009 |
| 7627848 |
Bit stream compatible FPGA to MPGA conversions |
Dec. 1, 2009 |
| 7620942 |
Method and system for parameterization of imperative-language functions intended as hardware generators |
Nov. 17, 2009 |
| 7619521 |
RFID network configuration program |
Nov. 17, 2009 |
| 7620918 |
Method and system for logic equivalence checking |
Nov. 17, 2009 |
| 7617535 |
Infected electronic system tracking |
Nov. 10, 2009 |
| 7613944 |
Programmable local clock buffer capable of varying initial settings |
Nov. 3, 2009 |
| 7614029 |
Methods and systems for converting a synchronous circuit fabric into an asynchronous dataflow circuit fabric |
Nov. 3, 2009 |
| 7610570 |
Method and mechanism for using systematic local search for SAT solving |
Oct. 27, 2009 |
| 7610566 |
Method and apparatus for function decomposition |
Oct. 27, 2009 |
| 7610567 |
Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs |
Oct. 27, 2009 |
| 7606774 |
Computer implemented cover process approximating quantifier elimination |
Oct. 20, 2009 |
| 7603647 |
Recognition of a state machine in high-level integrated circuit description language code |
Oct. 13, 2009 |
| 7603635 |
Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same |
Oct. 13, 2009 |
| 7600211 |
Toggle equivalence preserving logic synthesis |
Oct. 6, 2009 |
| 7596770 |
Temporal decomposition for design and verification |
Sep. 29, 2009 |
| 7594195 |
Multithreaded reachability |
Sep. 22, 2009 |
| 7594201 |
Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code |
Sep. 22, 2009 |
| 7594204 |
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays |
Sep. 22, 2009 |
| 7587687 |
System and method for incremental synthesis |
Sep. 8, 2009 |
| 7587688 |
User-directed timing-driven synthesis |
Sep. 8, 2009 |
| 7584460 |
Process and apparatus for abstracting IC design files |
Sep. 1, 2009 |
| 7584449 |
Logic synthesis of multi-level domino asynchronous pipelines |
Sep. 1, 2009 |
| 7577929 |
Early timing estimation of timing statistical properties of placement |
Aug. 18, 2009 |
| 7574684 |
Design data creating method, design data creating apparatus and computer readable information recording medium |
Aug. 11, 2009 |
| 7568173 |
Independent migration of hierarchical designs with methods of finding and fixing opens during migration |
Jul. 28, 2009 |
| 7565632 |
Behavioral synthesizer system, operation synthesizing method and program |
Jul. 21, 2009 |
| 7565631 |
Method and system for translating software binaries and assembly code onto hardware |
Jul. 21, 2009 |
| 7565636 |
System for performing verification of logic circuits |
Jul. 21, 2009 |
| 7562317 |
Multitasking circuit layout diagram silkscreen text handling method and system |
Jul. 14, 2009 |
| 7562322 |
Design verification for a switching network logic using formal techniques |
Jul. 14, 2009 |
| 7555739 |
Method and apparatus for maintaining synchronization between layout clones |
Jun. 30, 2009 |
| 7552405 |
Methods of implementing embedded processor systems including state machines |
Jun. 23, 2009 |
| 7546566 |
Method and system for verification of multi-voltage circuit design |
Jun. 9, 2009 |
| 7546565 |
Method for comparing two designs of electronic circuits |
Jun. 9, 2009 |
| 7546561 |
System and method of state point correspondence with constrained function determination |
Jun. 9, 2009 |
| 7546560 |
Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist |
Jun. 9, 2009 |
| 7543252 |
Migration of integrated circuit layout for alternating phase shift masks |
Jun. 2, 2009 |
| 7543253 |
Method and apparatus for compensating for temperature drift in semiconductor processes and circuitry |
Jun. 2, 2009 |
| 7539953 |
Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system |
May. 26, 2009 |
| 7539955 |
System and method for reformatting a motherboard design file |
May. 26, 2009 |
| 7539956 |
System and computer program product for simultaneous cell identification/technology mapping |
May. 26, 2009 |
| 7530047 |
Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass |
May. 5, 2009 |
| 7530037 |
Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods |
May. 5, 2009 |
| 7529858 |
Hard disk drive controller having versatile chip connector having printed circuit board engaged by at least two data ports having two pairs of differential connector elements |
May. 5, 2009 |
| 7523421 |
Method and apparatus for reducing the cost of multiplexer circuitry |
Apr. 21, 2009 |
| 7523423 |
Method and apparatus for production of data-flow-graphs by symbolic simulation |
Apr. 21, 2009 |
| 7519939 |
Method and program for supporting register-transfer-level design of semiconductor integrated circuit |
Apr. 14, 2009 |
| 7519930 |
Method of calculating a model formula for circuit simulation |
Apr. 14, 2009 |
| 7519931 |
Applying CNF simplification techniques for SAT-based abstraction refinement |
Apr. 14, 2009 |
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