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Class Information
Number: 716/2
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Optimization (e.g., redundancy, compaction)
Description: Subject matter comprising means or steps for improving the layout of the designed circuit components as far as possible.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620926 |
Methods and structures for flexible power management in integrated circuits |
Nov. 17, 2009 |
| 7620922 |
Method and system for optimized circuit autorouting |
Nov. 17, 2009 |
| 7620863 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits |
Nov. 17, 2009 |
| 7619521 |
RFID network configuration program |
Nov. 17, 2009 |
| 7617471 |
Processor event interface for programmable integrated circuit based circuit designs |
Nov. 10, 2009 |
| 7613942 |
Power mode transition in multi-threshold complementary metal oxide semiconductor (MTCMOS) circuits |
Nov. 3, 2009 |
| 7613599 |
Method and system for virtual prototyping |
Nov. 3, 2009 |
| 7610573 |
Implementation of alternate solutions in technology mapping and placement |
Oct. 27, 2009 |
| 7610566 |
Method and apparatus for function decomposition |
Oct. 27, 2009 |
| 7610565 |
Technology migration for integrated circuits with radical design restrictions |
Oct. 27, 2009 |
| 7607114 |
Designer's intent tolerance bands for proximity correction and checking |
Oct. 20, 2009 |
| 7607113 |
Wiring pattern determination method and computer program product thereof |
Oct. 20, 2009 |
| 7607112 |
Method and apparatus for performing metalization in an integrated circuit process |
Oct. 20, 2009 |
| 7606774 |
Computer implemented cover process approximating quantifier elimination |
Oct. 20, 2009 |
| 7606692 |
Gate-level netlist reduction for simulating target modules of a design |
Oct. 20, 2009 |
| 7603645 |
Calibration method of insulating washer in circuit board |
Oct. 13, 2009 |
| 7603641 |
Power/ground wire routing correction and optimization |
Oct. 13, 2009 |
| 7596769 |
Simulation of power domain isolation |
Sep. 29, 2009 |
| 7594213 |
Method and apparatus for computing dummy feature density for chemical-mechanical polishing |
Sep. 22, 2009 |
| 7594212 |
Automatic pin placement for integrated circuits to aid circuit board design |
Sep. 22, 2009 |
| 7594211 |
Methods and apparatuses for reset conditioning in integrated circuits |
Sep. 22, 2009 |
| 7594206 |
Fault detecting method and layout method for semiconductor integrated circuit |
Sep. 22, 2009 |
| 7594203 |
Parallel optimization using independent cell instances |
Sep. 22, 2009 |
| 7594202 |
Optimization of circuit designs using a continuous spectrum of library cells |
Sep. 22, 2009 |
| 7594201 |
Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code |
Sep. 22, 2009 |
| 7594200 |
Method for finding multi-cycle clock gating |
Sep. 22, 2009 |
| 7594199 |
Method of optical proximity correction design for contact hole mask |
Sep. 22, 2009 |
| 7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid |
Sep. 15, 2009 |
| 7590955 |
Method and system for implementing layout, placement, and routing with merged shapes |
Sep. 15, 2009 |
| 7587693 |
Apparatus and method of delay calculation for structured ASIC |
Sep. 8, 2009 |
| 7587687 |
System and method for incremental synthesis |
Sep. 8, 2009 |
| 7584449 |
Logic synthesis of multi-level domino asynchronous pipelines |
Sep. 1, 2009 |
| 7584445 |
Sequence-pair creating apparatus and sequence-pair creating method |
Sep. 1, 2009 |
| 7584440 |
Method and system for tuning a circuit |
Sep. 1, 2009 |
| 7581197 |
Relative positioning of circuit elements in circuit design |
Aug. 25, 2009 |
| 7577932 |
Gate modeling for semiconductor fabrication process effects |
Aug. 18, 2009 |
| 7577929 |
Early timing estimation of timing statistical properties of placement |
Aug. 18, 2009 |
| 7571422 |
Method for generating a design rule map having spatially varying overlay budget |
Aug. 4, 2009 |
| 7571420 |
Dynamic sampling with efficient model for overlay |
Aug. 4, 2009 |
| 7571404 |
Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noise |
Aug. 4, 2009 |
| 7571397 |
Method of design based process control optimization |
Aug. 4, 2009 |
| 7571396 |
System and method for providing swap path voltage and temperature compensation |
Aug. 4, 2009 |
| 7568179 |
Layout printability optimization method and system |
Jul. 28, 2009 |
| 7565634 |
Massively parallel boolean satisfiability implication circuit |
Jul. 21, 2009 |
| 7565632 |
Behavioral synthesizer system, operation synthesizing method and program |
Jul. 21, 2009 |
| 7565631 |
Method and system for translating software binaries and assembly code onto hardware |
Jul. 21, 2009 |
| RE40855 |
Integrated circuit having a reduced spacing between a bus and adjacent circuitry |
Jul. 14, 2009 |
| 7562325 |
Device to cluster Boolean functions for clock gating |
Jul. 14, 2009 |
| 7562322 |
Design verification for a switching network logic using formal techniques |
Jul. 14, 2009 |
| 7559045 |
Database-aided circuit design system and method therefor |
Jul. 7, 2009 |
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