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Class Information
Number: 716/19
Name: Data processing: design and analysis of circuit or semiconductor mask > Design of semiconductor mask
Description: Subject matter comprising means or steps for planning or devising a template used for etching circuit pattern on semiconductor wafers.

Sub-classes under this class:

Class Number Class Name Patents
716/20 Mesh generation 436
716/21 Pattern exposure 1,095

Patents under this class:

Patent Number Title Of Patent Date Issued
7805701 Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment Sep. 28, 2010
7805700 Physical-resist model using fast sweeping Sep. 28, 2010
7805699 Shape-based photolithographic model calibration Sep. 28, 2010
7805698 Methods and systems for physical hierarchy configuration engine and graphical editor Sep. 28, 2010
7802226 Data preparation for multiple mask printing Sep. 21, 2010
7802225 Optical proximity correction method, optical proximity correction apparatus, and optical proximity correction program, method of manufacturing semiconductor device, design rule formulating met Sep. 21, 2010
7802224 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium Sep. 21, 2010
7802218 Layout analysis method and apparatus for semiconductor integrated circuit Sep. 21, 2010
7801709 Simulation method using a simulation system that provides information on a transfer pattern of a predetermined mask pattern transferred to a wafer by optical photolithography and method of mod Sep. 21, 2010
7799489 Method for design and manufacture of a reticle using variable shaped beam lithography Sep. 21, 2010
7799487 Dual metric OPC Sep. 21, 2010
7797668 Method for optimally converting a circuit design into a semiconductor device Sep. 14, 2010
7797656 Method of checking and correcting mask pattern Sep. 14, 2010
7797646 Method for using mixed multi-Vt devices in a cell-based design Sep. 14, 2010
7793254 Method and system for designing a timing closure of an integrated circuit Sep. 7, 2010
7793253 Mask-patterns including intentional breaks Sep. 7, 2010
7793238 Method and apparatus for improving a circuit layout using a hierarchical layout description Sep. 7, 2010
7788630 Method and apparatus for determining an optical model that models the effect of optical proximity correction Aug. 31, 2010
7788629 Systems configured to perform a non-contact method for determining a property of a specimen Aug. 31, 2010
7788628 Computational efficiency in photolithographic process simulation Aug. 31, 2010
7788627 Lithography verification using guard bands Aug. 31, 2010
7788626 Pattern data correction method, pattern checking method, pattern check program, photo mask producing method, and semiconductor device manufacturing method Aug. 31, 2010
7788612 System, method, and computer program product for matching cell layout of an integrated circuit design Aug. 31, 2010
7785946 Integrated circuits and methods of design and manufacture thereof Aug. 31, 2010
7784020 Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device Aug. 24, 2010
7784019 Yield based retargeting for semiconductor design flow Aug. 24, 2010
7784018 Method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model Aug. 24, 2010
7784017 Lithography simulation method, photomask manufacturing method, semiconductor device manufacturing method, and recording medium Aug. 24, 2010
7784016 Method and system for context-specific mask writing Aug. 24, 2010
7784015 Method for generating a mask layout and constructing an integrated circuit Aug. 24, 2010
7784009 Electrically programmable .pi.-shaped fuse structures and design process therefore Aug. 24, 2010
7784001 Circuit design method, circuit design system, and program product for causing computer to perform circuit design Aug. 24, 2010
RE41548 FPGA with hybrid interconnect Aug. 17, 2010
7776628 Method and system for tone inverting of residual layer tolerant imprint lithography Aug. 17, 2010
7774739 Methods for adjusting shifter width of an alternating phase shifter having variable width Aug. 10, 2010
7774738 Lithography method for forming a circuit pattern Aug. 10, 2010
7774737 Performance in model-based OPC engine utilizing efficient polygon pinning method Aug. 10, 2010
7774736 Method and apparatus for providing optical proximity features to a reticle pattern for deep sub-wavelength optical lithography Aug. 10, 2010
7771901 Layout method for mask Aug. 10, 2010
7771604 Reduced mask count gate conductor definition Aug. 10, 2010
7770144 Modular array defined by standard cell logic Aug. 3, 2010
7767515 Managing integrated circuit stress using stress adjustment trenches Aug. 3, 2010
7765518 System and method for implementing optical rule checking to identify and quantify corner rounding errors Jul. 27, 2010
7765517 Method and apparatus for removing dummy features from a data structure Jul. 27, 2010
7765516 System and method for making photomasks Jul. 27, 2010
7765515 Pattern match based optical proximity correction and verification of integrated circuit layout Jul. 27, 2010
7765021 Method to check model accuracy during wafer patterning simulation Jul. 27, 2010
7763918 Image pixel design to enhance the uniformity of intensity distribution on digital image sensors Jul. 27, 2010
7763398 Layout method for mask Jul. 27, 2010
7761839 Performance in model-based OPC engine utilizing efficient polygon pinning method Jul. 20, 2010

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