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Class Information
Number: 716/18
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Logical circuit synthesizer
Description: Subject matter comprising means or steps for automatically transforming a high-level design (e.g., functional specification or functional-level logic such as Boolean expression, truth table, or standard macro logic) into its hardware implementation.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620942 |
Method and system for parameterization of imperative-language functions intended as hardware generators |
Nov. 17, 2009 |
| 7620929 |
Programmable logic device having a programmable selector circuit |
Nov. 17, 2009 |
| 7620928 |
Method and apparatus for synthesizing a hardware system from a software description |
Nov. 17, 2009 |
| 7620927 |
Method and apparatus for circuit design closure using partitions |
Nov. 17, 2009 |
| 7620926 |
Methods and structures for flexible power management in integrated circuits |
Nov. 17, 2009 |
| 7620925 |
Method and apparatus for performing post-placement routability optimization |
Nov. 17, 2009 |
| 7620924 |
Base platforms with combined ASIC and FPGA features and process of using the same |
Nov. 17, 2009 |
| 7620922 |
Method and system for optimized circuit autorouting |
Nov. 17, 2009 |
| 7620917 |
Methods and apparatuses for automated circuit design |
Nov. 17, 2009 |
| 7620863 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits |
Nov. 17, 2009 |
| 7617472 |
Regional signal-distribution network for an integrated circuit |
Nov. 10, 2009 |
| 7617471 |
Processor event interface for programmable integrated circuit based circuit designs |
Nov. 10, 2009 |
| 7614029 |
Methods and systems for converting a synchronous circuit fabric into an asynchronous dataflow circuit fabric |
Nov. 3, 2009 |
| 7613599 |
Method and system for virtual prototyping |
Nov. 3, 2009 |
| 7610573 |
Implementation of alternate solutions in technology mapping and placement |
Oct. 27, 2009 |
| 7610571 |
Method and system for simulating state retention of an RTL design |
Oct. 27, 2009 |
| 7610569 |
Chip design verification apparatus and data communication method for the same |
Oct. 27, 2009 |
| 7603647 |
Recognition of a state machine in high-level integrated circuit description language code |
Oct. 13, 2009 |
| 7603646 |
Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables |
Oct. 13, 2009 |
| 7603639 |
Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry |
Oct. 13, 2009 |
| 7603636 |
Assertion generating system, program thereof, circuit verifying system, and assertion generating method |
Oct. 13, 2009 |
| 7600211 |
Toggle equivalence preserving logic synthesis |
Oct. 6, 2009 |
| RE40925 |
Methods for automatically pipelining loops |
Sep. 29, 2009 |
| 7596772 |
Methodology and system for setup/hold time characterization of analog IP |
Sep. 29, 2009 |
| 7596769 |
Simulation of power domain isolation |
Sep. 29, 2009 |
| 7594208 |
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage |
Sep. 22, 2009 |
| 7594200 |
Method for finding multi-cycle clock gating |
Sep. 22, 2009 |
| 7590965 |
Methods of generating a design architecture tailored to specified requirements of a PLD design |
Sep. 15, 2009 |
| 7590964 |
Method and system for automatic generation of processor datapaths using instruction set architecture implementing means |
Sep. 15, 2009 |
| 7587698 |
Operational time extension |
Sep. 8, 2009 |
| 7587697 |
System and method of mapping memory blocks in a configurable integrated circuit |
Sep. 8, 2009 |
| 7587688 |
User-directed timing-driven synthesis |
Sep. 8, 2009 |
| 7584460 |
Process and apparatus for abstracting IC design files |
Sep. 1, 2009 |
| 7584449 |
Logic synthesis of multi-level domino asynchronous pipelines |
Sep. 1, 2009 |
| 7584448 |
Constructing a model of a programmable logic device |
Sep. 1, 2009 |
| 7584437 |
Assuring correct data entry to generate shells for a semiconductor platform |
Sep. 1, 2009 |
| 7581201 |
System and method for sign-off timing closure of a VLSI chip |
Aug. 25, 2009 |
| 7576569 |
Circuit for dynamic circuit timing synthesis and monitoring of critical paths and environmental conditions of an integrated circuit |
Aug. 18, 2009 |
| 7574688 |
Using high-level language functions in HDL synthesis tools |
Aug. 11, 2009 |
| 7571422 |
Method for generating a design rule map having spatially varying overlay budget |
Aug. 4, 2009 |
| 7571416 |
Automatic design device, method, and program for semiconductor integrated circuits |
Aug. 4, 2009 |
| 7571414 |
Multi-project system-on-chip and its method |
Aug. 4, 2009 |
| 7571404 |
Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noise |
Aug. 4, 2009 |
| 7571396 |
System and method for providing swap path voltage and temperature compensation |
Aug. 4, 2009 |
| 7568178 |
System simulation and graphical data flow programming in a common environment using wire data flow |
Jul. 28, 2009 |
| 7568173 |
Independent migration of hierarchical designs with methods of finding and fixing opens during migration |
Jul. 28, 2009 |
| 7565638 |
Density-based layer filler for integrated circuit design |
Jul. 21, 2009 |
| 7565632 |
Behavioral synthesizer system, operation synthesizing method and program |
Jul. 21, 2009 |
| 7562322 |
Design verification for a switching network logic using formal techniques |
Jul. 14, 2009 |
| 7562321 |
Method and apparatus for structured ASIC test point insertion |
Jul. 14, 2009 |
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