| |
 |
|
Class Information
Number: 716/17
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)
Description: Subject matter wherein the designed circuit utilizes a high-level circuit element such as an arithmetic or logical component selectively operable (i.e., programmable component) to perform a given or required specific combinational function.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620863 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits |
Nov. 17, 2009 |
| 7620924 |
Base platforms with combined ASIC and FPGA features and process of using the same |
Nov. 17, 2009 |
| 7620926 |
Methods and structures for flexible power management in integrated circuits |
Nov. 17, 2009 |
| 7620929 |
Programmable logic device having a programmable selector circuit |
Nov. 17, 2009 |
| 7617470 |
Reconfigurable integrated circuit and method for increasing performance of a reconfigurable integrated circuit |
Nov. 10, 2009 |
| 7617471 |
Processor event interface for programmable integrated circuit based circuit designs |
Nov. 10, 2009 |
| 7617472 |
Regional signal-distribution network for an integrated circuit |
Nov. 10, 2009 |
| 7614020 |
Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems |
Nov. 3, 2009 |
| 7614022 |
Testing for bridge faults in the interconnect of programmable integrated circuits |
Nov. 3, 2009 |
| 7614027 |
Methods for forming a MRAM with non-orthogonal wiring |
Nov. 3, 2009 |
| 7607117 |
Representing device layout using tree structure |
Oct. 20, 2009 |
| 7607005 |
Virtual hardware system with universal ports using FPGA |
Oct. 20, 2009 |
| 7603599 |
Method to test routed networks |
Oct. 13, 2009 |
| 7603646 |
Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables |
Oct. 13, 2009 |
| 7596775 |
Method for determining a standard cell for IC design |
Sep. 29, 2009 |
| 7596774 |
Hard macro with configurable side input/output terminals, for a subsystem |
Sep. 29, 2009 |
| 7594211 |
Methods and apparatuses for reset conditioning in integrated circuits |
Sep. 22, 2009 |
| 7590965 |
Methods of generating a design architecture tailored to specified requirements of a PLD design |
Sep. 15, 2009 |
| 7590960 |
Placing partitioned circuit designs within iterative implementation flows |
Sep. 15, 2009 |
| 7590951 |
Plug-in component-based dependency management for partitions within an incremental implementation flow |
Sep. 15, 2009 |
| 7587686 |
Clock gating in a structured ASIC |
Sep. 8, 2009 |
| 7587699 |
Automated system for designing and developing field programmable gate arrays |
Sep. 8, 2009 |
| 7584447 |
PLD architecture for flexible placement of IP function blocks |
Sep. 1, 2009 |
| 7574679 |
Generating cores using secure scripts |
Aug. 11, 2009 |
| 7574680 |
Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip |
Aug. 11, 2009 |
| 7574681 |
Method and system for evaluating computer program tests by means of mutation analysis |
Aug. 11, 2009 |
| 7571415 |
Layout of power device |
Aug. 4, 2009 |
| 7571414 |
Multi-project system-on-chip and its method |
Aug. 4, 2009 |
| 7571395 |
Generation of a circuit design from a command language specification of blocks in matrix form |
Aug. 4, 2009 |
| 7568172 |
Integration of pre-defined functionality and a graphical program in a circuit |
Jul. 28, 2009 |
| 7562162 |
Systems and methods for distributed computing utilizing a smart memory apparatus |
Jul. 14, 2009 |
| 7562324 |
Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization |
Jul. 14, 2009 |
| 7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a substrate |
Jul. 14, 2009 |
| 7562331 |
Netlist synthesis and automatic generation of PC board schematics |
Jul. 14, 2009 |
| 7562332 |
Disabling unused/inactive resources in programmable logic devices for static power reduction |
Jul. 14, 2009 |
| 7558967 |
Encryption for a stream file in an FPGA integrated circuit |
Jul. 7, 2009 |
| 7558969 |
Anti-pirate circuit for protection against commercial integrated circuit pirates |
Jul. 7, 2009 |
| 7559045 |
Database-aided circuit design system and method therefor |
Jul. 7, 2009 |
| 7555738 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Jun. 30, 2009 |
| 7549139 |
Tuning programmable logic devices for low-power design implementation |
Jun. 16, 2009 |
| 7546556 |
Virtual shape based parameterized cell |
Jun. 9, 2009 |
| 7546394 |
Management of configuration data by generating a chain description data set that specifies an order of configuration chain for multi-device systems |
Jun. 9, 2009 |
| 7546570 |
Communications bus for a parallel processing system |
Jun. 9, 2009 |
| 7543283 |
Flexible instruction processor systems and methods |
Jun. 2, 2009 |
| 7543265 |
Method for early logic mapping during FPGA synthesis |
Jun. 2, 2009 |
| 7539967 |
Self-configuring components on a device |
May. 26, 2009 |
| 7539953 |
Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system |
May. 26, 2009 |
| 7536668 |
Determining networks of a tile module of a programmable logic device |
May. 19, 2009 |
| 7536615 |
Logic analyzer systems and methods for programmable logic devices |
May. 19, 2009 |
| 7536669 |
Generic DMA IP core interface for FPGA platform design |
May. 19, 2009 |
|
|
|
