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Class Information
Number: 716/16
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Routing (e.g., routing map, netlisting) > Pla, pld, fpga, or mcm
Description: Subject matter wherein the circuit components are programmable logic arrays or devices, field programmable gate arrays, or multichip modules.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620853 |
Methods for detecting resistive bridging faults at configuration random-access memory output nodes |
Nov. 17, 2009 |
| 7620924 |
Base platforms with combined ASIC and FPGA features and process of using the same |
Nov. 17, 2009 |
| 7620925 |
Method and apparatus for performing post-placement routability optimization |
Nov. 17, 2009 |
| 7620926 |
Methods and structures for flexible power management in integrated circuits |
Nov. 17, 2009 |
| 7620927 |
Method and apparatus for circuit design closure using partitions |
Nov. 17, 2009 |
| 7616508 |
Flash-based FPGA with secure reprogramming |
Nov. 10, 2009 |
| 7617472 |
Regional signal-distribution network for an integrated circuit |
Nov. 10, 2009 |
| 7617470 |
Reconfigurable integrated circuit and method for increasing performance of a reconfigurable integrated circuit |
Nov. 10, 2009 |
| 7616027 |
Configurable circuits, IC's and systems |
Nov. 10, 2009 |
| 7613858 |
Implementing signal processing cores as application specific processors |
Nov. 3, 2009 |
| 7614020 |
Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems |
Nov. 3, 2009 |
| 7614029 |
Methods and systems for converting a synchronous circuit fabric into an asynchronous dataflow circuit fabric |
Nov. 3, 2009 |
| 7610572 |
Semiconductor integrated circuit device with independent power domains |
Oct. 27, 2009 |
| 7607118 |
Techniques for using edge masks to perform timing analysis |
Oct. 20, 2009 |
| 7607117 |
Representing device layout using tree structure |
Oct. 20, 2009 |
| 7607005 |
Virtual hardware system with universal ports using FPGA |
Oct. 20, 2009 |
| 7602212 |
Flexible high-speed serial interface architectures for programmable integrated circuit devices |
Oct. 13, 2009 |
| 7603599 |
Method to test routed networks |
Oct. 13, 2009 |
| 7603646 |
Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables |
Oct. 13, 2009 |
| 7598768 |
Method and apparatus for dynamic port provisioning within a programmable logic device |
Oct. 6, 2009 |
| 7600210 |
Method and apparatus for modular circuit design for a programmable logic device |
Oct. 6, 2009 |
| 7595655 |
Retrieving data from a configurable IC |
Sep. 29, 2009 |
| 7594046 |
Data processing in which concurrently executed processes communicate via a FIFO buffer |
Sep. 22, 2009 |
| 7594204 |
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays |
Sep. 22, 2009 |
| 7594212 |
Automatic pin placement for integrated circuits to aid circuit board design |
Sep. 22, 2009 |
| 7590960 |
Placing partitioned circuit designs within iterative implementation flows |
Sep. 15, 2009 |
| 7590951 |
Plug-in component-based dependency management for partitions within an incremental implementation flow |
Sep. 15, 2009 |
| 7590965 |
Methods of generating a design architecture tailored to specified requirements of a PLD design |
Sep. 15, 2009 |
| 7587686 |
Clock gating in a structured ASIC |
Sep. 8, 2009 |
| 7587697 |
System and method of mapping memory blocks in a configurable integrated circuit |
Sep. 8, 2009 |
| 7587698 |
Operational time extension |
Sep. 8, 2009 |
| 7584448 |
Constructing a model of a programmable logic device |
Sep. 1, 2009 |
| 7584447 |
PLD architecture for flexible placement of IP function blocks |
Sep. 1, 2009 |
| 7584446 |
Method and apparatus for extending processing time in one pipeline stage |
Sep. 1, 2009 |
| 7584460 |
Process and apparatus for abstracting IC design files |
Sep. 1, 2009 |
| 7577929 |
Early timing estimation of timing statistical properties of placement |
Aug. 18, 2009 |
| 7574687 |
Method and system to optimize timing margin in a system in package module |
Aug. 11, 2009 |
| 7574679 |
Generating cores using secure scripts |
Aug. 11, 2009 |
| 7573296 |
Configurable IC with configurable routing resources that have asymmetric input and/or outputs |
Aug. 11, 2009 |
| 7571395 |
Generation of a circuit design from a command language specification of blocks in matrix form |
Aug. 4, 2009 |
| 7571412 |
Method and system for semiconductor device characterization pattern generation and analysis |
Aug. 4, 2009 |
| 7571413 |
Testing circuitry for programmable logic devices with selectable power supply voltages |
Aug. 4, 2009 |
| 7565635 |
SiP (system in package) design systems and methods |
Jul. 21, 2009 |
| 7565634 |
Massively parallel boolean satisfiability implication circuit |
Jul. 21, 2009 |
| 7565280 |
Solver for simulating a system in real time on a programmable hardware element |
Jul. 21, 2009 |
| 7562162 |
Systems and methods for distributed computing utilizing a smart memory apparatus |
Jul. 14, 2009 |
| 7562331 |
Netlist synthesis and automatic generation of PC board schematics |
Jul. 14, 2009 |
| 7562332 |
Disabling unused/inactive resources in programmable logic devices for static power reduction |
Jul. 14, 2009 |
| 7562350 |
Processing system and method using recomposable software |
Jul. 14, 2009 |
| 7558967 |
Encryption for a stream file in an FPGA integrated circuit |
Jul. 7, 2009 |
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