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Class Information
Number: 716/12
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Routing (e.g., routing map, netlisting)
Description: Subject matter comprising means or steps for determining the interconnections or path nets between circuit blocks or circuit components and input/output bonding pads (pins).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7627847 |
Method and system for representing manufacturing and lithography information for IC routing |
Dec. 1, 2009 |
| 7627846 |
Method and apparatus for automatically shaping traces on surface of substrate of semiconductor package by using computation |
Dec. 1, 2009 |
| 7627845 |
Macrocell, integrated circuit device, and electronic instrument |
Dec. 1, 2009 |
| 7624367 |
Method and system for routing |
Nov. 24, 2009 |
| 7624361 |
Method and device for designing semiconductor integrated circuit |
Nov. 24, 2009 |
| 7622779 |
Interconnection architecture and method of assessing interconnection architecture |
Nov. 24, 2009 |
| 7620923 |
Run-time efficient methods for routing large multi-fanout nets |
Nov. 17, 2009 |
| 7617467 |
Electrostatic discharge device verification in an integrated circuit |
Nov. 10, 2009 |
| 7617463 |
Power supply method for semiconductor integrated circuit in test and CAD system for semiconductor integrated circuit |
Nov. 10, 2009 |
| 7614028 |
Representation, configuration, and reconfiguration of routing method and system |
Nov. 3, 2009 |
| 7614027 |
Methods for forming a MRAM with non-orthogonal wiring |
Nov. 3, 2009 |
| 7614025 |
Method of placement for iterative implementation flows |
Nov. 3, 2009 |
| 7607118 |
Techniques for using edge masks to perform timing analysis |
Oct. 20, 2009 |
| 7607113 |
Wiring pattern determination method and computer program product thereof |
Oct. 20, 2009 |
| 7603644 |
Integrated circuit routing and compaction |
Oct. 13, 2009 |
| 7603642 |
Placer with wires for RF and analog design |
Oct. 13, 2009 |
| 7603634 |
Various methods and apparatuses to preserve a logic state for a volatile latch circuit |
Oct. 13, 2009 |
| 7603599 |
Method to test routed networks |
Oct. 13, 2009 |
| 7595655 |
Retrieving data from a configurable IC |
Sep. 29, 2009 |
| 7594215 |
Method and system for optimized automated IC package pin routing |
Sep. 22, 2009 |
| 7594214 |
Maximum flow analysis for electronic circuit design |
Sep. 22, 2009 |
| 7594207 |
Computationally efficient design rule checking for circuit interconnect routing design |
Sep. 22, 2009 |
| 7594206 |
Fault detecting method and layout method for semiconductor integrated circuit |
Sep. 22, 2009 |
| 7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus |
Sep. 22, 2009 |
| 7590960 |
Placing partitioned circuit designs within iterative implementation flows |
Sep. 15, 2009 |
| 7587699 |
Automated system for designing and developing field programmable gate arrays |
Sep. 8, 2009 |
| 7587693 |
Apparatus and method of delay calculation for structured ASIC |
Sep. 8, 2009 |
| 7584448 |
Constructing a model of a programmable logic device |
Sep. 1, 2009 |
| 7584447 |
PLD architecture for flexible placement of IP function blocks |
Sep. 1, 2009 |
| 7581201 |
System and method for sign-off timing closure of a VLSI chip |
Aug. 25, 2009 |
| 7581200 |
System and method for analyzing length differences in differential signal paths |
Aug. 25, 2009 |
| 7581198 |
Method and system for the modular design and layout of integrated circuits |
Aug. 25, 2009 |
| 7581197 |
Relative positioning of circuit elements in circuit design |
Aug. 25, 2009 |
| 7580824 |
Apparatus and methods for modeling power characteristics of electronic circuitry |
Aug. 25, 2009 |
| 7577932 |
Gate modeling for semiconductor fabrication process effects |
Aug. 18, 2009 |
| 7574686 |
Method and system for implementing deterministic multi-processing |
Aug. 11, 2009 |
| 7571418 |
Simulation site placement for lithographic process models |
Aug. 4, 2009 |
| 7571415 |
Layout of power device |
Aug. 4, 2009 |
| 7571412 |
Method and system for semiconductor device characterization pattern generation and analysis |
Aug. 4, 2009 |
| 7571411 |
Methods and apparatus for providing flexible timing-driven routing trees |
Aug. 4, 2009 |
| 7571410 |
Resonant tree driven clock distribution grid |
Aug. 4, 2009 |
| 7571409 |
Circuit design device and circuit design program |
Aug. 4, 2009 |
| 7565638 |
Density-based layer filler for integrated circuit design |
Jul. 21, 2009 |
| 7562330 |
Budgeting global constraints on local constraints in an autorouter |
Jul. 14, 2009 |
| 7562329 |
Master-slice-type semiconductor integrated circuit having a bulk layer and a plurality of wiring layers and a design method therefor |
Jul. 14, 2009 |
| 7561534 |
Methods of network routing having improved resistance to faults affecting groups of links subject to common risks |
Jul. 14, 2009 |
| 7561487 |
Layout technique for address signal lines in decoders including stitched blocks |
Jul. 14, 2009 |
| 7559044 |
Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit |
Jul. 7, 2009 |
| 7559042 |
Layout evaluating apparatus |
Jul. 7, 2009 |
| 7559040 |
Optimization of combinational logic synthesis through clock latency scheduling |
Jul. 7, 2009 |
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