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Class Information
Number: 716/12
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Routing (e.g., routing map, netlisting)
Description: Subject matter comprising means or steps for determining the interconnections or path nets between circuit blocks or circuit components and input/output bonding pads (pins).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7415688 |
Method of manufacturing surface-emitting backlight, by molding contact member integrally with molded case |
Aug. 19, 2008 |
| 7415687 |
Method and computer program for incremental placement and routing with nested shells |
Aug. 19, 2008 |
| 7412681 |
DC path checking in a hierarchical circuit design |
Aug. 12, 2008 |
| 7409663 |
Process for the production of an electrical wiring diagram |
Aug. 5, 2008 |
| 7409664 |
Architecture and interconnect scheme for programmable logic circuits |
Aug. 5, 2008 |
| 7409662 |
Systems and methods involving designing shielding profiles for integrated circuits |
Aug. 5, 2008 |
| 7409659 |
System and method for suppressing crosstalk glitch in digital circuits |
Aug. 5, 2008 |
| 7408382 |
Configurable circuits, IC's, and systems |
Aug. 5, 2008 |
| 7406669 |
Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models |
Jul. 29, 2008 |
| 7404161 |
Fullchip functional equivalency and physical verification |
Jul. 22, 2008 |
| 7404162 |
Buffering technique using structured delay skewing |
Jul. 22, 2008 |
| 7404166 |
Method and system for mapping netlist of integrated circuit to design |
Jul. 22, 2008 |
| 7401317 |
Method and system for rapidly identifying silicon manufacturing defects |
Jul. 15, 2008 |
| 7401313 |
Method and apparatus for controlling congestion during integrated circuit design resynthesis |
Jul. 15, 2008 |
| 7401312 |
Automatic method for routing and designing an LSI |
Jul. 15, 2008 |
| 7401308 |
Timing analysis apparatus, timing analysis method, and computer product |
Jul. 15, 2008 |
| 7398506 |
Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing |
Jul. 8, 2008 |
| 7398499 |
Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design |
Jul. 8, 2008 |
| 7398498 |
Method and apparatus for storing routes for groups of related net configurations |
Jul. 8, 2008 |
| 7398492 |
Rules and directives for validating correct data used in the design of semiconductor products |
Jul. 8, 2008 |
| 7398485 |
Yield optimization in router for systematic defects |
Jul. 8, 2008 |
| 7398380 |
Dynamic hardware partitioning of symmetric multiprocessing systems |
Jul. 8, 2008 |
| 7397256 |
Automatic design method for semiconductor device |
Jul. 8, 2008 |
| 7392499 |
Placement of input/output blocks of an electronic design in an integrated circuit |
Jun. 24, 2008 |
| 7392497 |
Regular routing for deep sub-micron chip design |
Jun. 24, 2008 |
| 7392169 |
Method, system and program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language |
Jun. 24, 2008 |
| 7389485 |
Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures |
Jun. 17, 2008 |
| 7386776 |
System for testing digital components |
Jun. 10, 2008 |
| 7383527 |
Semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus |
Jun. 3, 2008 |
| 7380231 |
Wire spreading through geotopological layout |
May. 27, 2008 |
| 7378874 |
Creating high-drive logic devices from standard gates with minimal use of custom masks |
May. 27, 2008 |
| 7380233 |
Method of facilitating integrated circuit design using manufactured property values |
May. 27, 2008 |
| 7376928 |
Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure |
May. 20, 2008 |
| 7376927 |
Manhattan routing with minimized distance to destination points |
May. 20, 2008 |
| 7376926 |
Run-time efficient methods for routing large multi-fanout nets |
May. 20, 2008 |
| 7376925 |
Method for production of a standard cell arrangement, and apparatus for carrying out the method |
May. 20, 2008 |
| 7376924 |
Methods for placement which maintain optimized behavior, while improving wireability potential |
May. 20, 2008 |
| 7373216 |
Method and apparatus for verifying a site-dependent wafer |
May. 13, 2008 |
| 7370314 |
Method and program for generating layout data of a semiconductor integrated circuit and method for manufacturing a semiconductor integrated circuit with optical proximity correction |
May. 6, 2008 |
| 7370309 |
Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints |
May. 6, 2008 |
| 7370308 |
Integrated circuit analysis method and program product |
May. 6, 2008 |
| 7370307 |
Computer automated design system, a computer automated design method, and a semiconductor integrated circuit |
May. 6, 2008 |
| 7368943 |
Enhanced scheme to implement an interconnection fabric using switching networks in hierarchy |
May. 6, 2008 |
| 7366997 |
Methods and apparatuses for thermal analysis based circuit design |
Apr. 29, 2008 |
| 7360177 |
Method and arrangement providing for implementation granularity using implementation sets |
Apr. 15, 2008 |
| 7360192 |
Macrocell, integrated circuit device, and electronic instrument |
Apr. 15, 2008 |
| 7356798 |
Semiconductor integrated circuit routing method and recording medium which stores routing software |
Apr. 8, 2008 |
| 7353490 |
Power network synthesizer for an integrated circuit design |
Apr. 1, 2008 |
| 7353476 |
System, method and computer program product for designing connecting terminals of semiconductor device |
Apr. 1, 2008 |
| 7353480 |
Apparatus, system, and method for designing via pads having extended contours |
Apr. 1, 2008 |
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