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Class Information
Number: 716/11
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Floorplanning > Layout editor (e.g., updating)
Description: Subject matter comprising means or steps for revising or modifying the circuit layout interactively by utilizing graphical representations such as icons or menus.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7619521 |
RFID network configuration program |
Nov. 17, 2009 |
| 7617535 |
Infected electronic system tracking |
Nov. 10, 2009 |
| 7617467 |
Electrostatic discharge device verification in an integrated circuit |
Nov. 10, 2009 |
| 7617465 |
Method and mechanism for performing latch-up check on an IC design |
Nov. 10, 2009 |
| 7614033 |
Mask data preparation |
Nov. 3, 2009 |
| 7614026 |
Pattern forming method, computer program thereof, and semiconductor device manufacturing method using the computer program |
Nov. 3, 2009 |
| 7614025 |
Method of placement for iterative implementation flows |
Nov. 3, 2009 |
| 7614024 |
Method to implement metal fill during integrated circuit design and layout |
Nov. 3, 2009 |
| 7610568 |
Methods and apparatus for making placement sensitive logic modifications |
Oct. 27, 2009 |
| 7607114 |
Designer's intent tolerance bands for proximity correction and checking |
Oct. 20, 2009 |
| 7607113 |
Wiring pattern determination method and computer program product thereof |
Oct. 20, 2009 |
| 7603640 |
Multilevel IC floorplanner |
Oct. 13, 2009 |
| 7600208 |
Automatic placement of decoupling capacitors |
Oct. 6, 2009 |
| 7600207 |
Stress-managed revision of integrated circuit layouts |
Oct. 6, 2009 |
| 7600205 |
Net/wiring selection method, net selection method, wiring selection method, and delay improvement method |
Oct. 6, 2009 |
| 7596771 |
Distributed element generator, method of generating distributed elements and an electronic design automation tool employing the same |
Sep. 29, 2009 |
| 7590962 |
Design method and architecture for power gate switch placement |
Sep. 15, 2009 |
| 7590960 |
Placing partitioned circuit designs within iterative implementation flows |
Sep. 15, 2009 |
| 7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid |
Sep. 15, 2009 |
| 7590955 |
Method and system for implementing layout, placement, and routing with merged shapes |
Sep. 15, 2009 |
| 7587703 |
Layout determination method, method of manufacturing semiconductor devices, and computer readable program |
Sep. 8, 2009 |
| 7587695 |
Protection boundaries in a parallel printed circuit board design environment |
Sep. 8, 2009 |
| 7587694 |
System and method for utilizing meta-cells |
Sep. 8, 2009 |
| 7581200 |
System and method for analyzing length differences in differential signal paths |
Aug. 25, 2009 |
| 7581198 |
Method and system for the modular design and layout of integrated circuits |
Aug. 25, 2009 |
| 7581197 |
Relative positioning of circuit elements in circuit design |
Aug. 25, 2009 |
| 7574685 |
Method, system, and article of manufacture for reducing via failures in an integrated circuit design |
Aug. 11, 2009 |
| 7574684 |
Design data creating method, design data creating apparatus and computer readable information recording medium |
Aug. 11, 2009 |
| 7574683 |
Automating power domains in electronic design automation |
Aug. 11, 2009 |
| 7571420 |
Dynamic sampling with efficient model for overlay |
Aug. 4, 2009 |
| 7571418 |
Simulation site placement for lithographic process models |
Aug. 4, 2009 |
| 7571410 |
Resonant tree driven clock distribution grid |
Aug. 4, 2009 |
| 7571397 |
Method of design based process control optimization |
Aug. 4, 2009 |
| 7568178 |
System simulation and graphical data flow programming in a common environment using wire data flow |
Jul. 28, 2009 |
| 7565638 |
Density-based layer filler for integrated circuit design |
Jul. 21, 2009 |
| 7562328 |
Navigation tool for connectors |
Jul. 14, 2009 |
| 7562327 |
Mask layout design improvement in gate width direction |
Jul. 14, 2009 |
| 7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a substrate |
Jul. 14, 2009 |
| 7562317 |
Multitasking circuit layout diagram silkscreen text handling method and system |
Jul. 14, 2009 |
| 7559046 |
Circuit design tools with optimization assistance |
Jul. 7, 2009 |
| 7559044 |
Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit |
Jul. 7, 2009 |
| 7559042 |
Layout evaluating apparatus |
Jul. 7, 2009 |
| 7555739 |
Method and apparatus for maintaining synchronization between layout clones |
Jun. 30, 2009 |
| 7549137 |
Latch placement for high performance and low power circuits |
Jun. 16, 2009 |
| 7546571 |
Distributed electronic design automation environment |
Jun. 9, 2009 |
| 7546568 |
Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage |
Jun. 9, 2009 |
| 7546559 |
Method of optimization of clock gating in integrated circuit designs |
Jun. 9, 2009 |
| 7543263 |
Automatic trace shaping method |
Jun. 2, 2009 |
| 7543262 |
Analog layout module generator and method |
Jun. 2, 2009 |
| 7543261 |
I/O planning with lock and insertion features |
Jun. 2, 2009 |
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