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Class Information
Number: 716/108
Name: Data processing: design and analysis of circuit or semiconductor mask >

Sub-classes under this class:

Class Number Class Name Patents
716/ Applications (364/400) 0
716/1 Circuit design 1,972
716/19 Design of semiconductor mask 1,426

Patents under this class:

Patent Number Title Of Patent Date Issued
8712752 IR(voltage) drop analysis in integrated circuit timing Apr. 29, 2014
8713496 Specification of latency in programmable device configuration Apr. 29, 2014
8707228 Method and system for implementing hierarchical prototyping of electronic designs Apr. 22, 2014
8707233 Systems and methods for correlated parameters in statistical static timing analysis Apr. 22, 2014
8707234 Circuit noise extraction using forced input noise waveform Apr. 22, 2014
8694937 Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same Apr. 8, 2014
8689170 Changing the location of a buffer bay in a netlist Apr. 1, 2014
8689154 Providing timing-closed FinFET designs from planar designs Apr. 1, 2014
8683409 Performing statistical timing analysis with non-separable statistical and deterministic variations Mar. 25, 2014
8683401 Information processing device and design supporting method Mar. 25, 2014
8683402 Clock alias for timing analysis of an integrated circuit design Mar. 25, 2014
8677305 Designing a robust power efficient clock distribution network Mar. 18, 2014
8677295 Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design Mar. 18, 2014
8677294 Semiconductor device, adjustment method thereof and data processing system Mar. 18, 2014
8671374 Information processing apparatus Mar. 11, 2014
8667449 Flip-flop library development for high frequency designs built in an ASIC flow Mar. 4, 2014
8667448 Integrated circuit having local maximum operating voltage Mar. 4, 2014
8667439 Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost Mar. 4, 2014
8667438 Optimization of library slew ratio based circuit Mar. 4, 2014
8661383 VLSI black-box verification Feb. 25, 2014
8661384 Verification support apparatus, verifying apparatus, computer product, verification support method, and verifying method Feb. 25, 2014
8661386 Method and apparatus for performing timing analysis with current source driver models using interpolated device characteristics Feb. 25, 2014
8656340 Delay analysis apparatus, computer-readable recording medium having delay analysis program stored thereon, and delay analysis method Feb. 18, 2014
8656332 Automated critical area allocation in a physical synthesized hierarchical design Feb. 18, 2014
8656329 System and method for implementing power integrity topology adapted for parametrically integrated environment Feb. 18, 2014
8656324 Circuit design systems for replacing flip-flops with pulsed latches Feb. 18, 2014
8650519 Automated functional coverage for an integrated circuit design Feb. 11, 2014
8645884 Multi-layer memory structure for behavioral modeling in a pre-distorter Feb. 4, 2014
8645883 Integrated circuit simulation using fundamental and derivative circuit runs Feb. 4, 2014
8645117 Clock simulation device and methods thereof Feb. 4, 2014
8645885 Specification of multithreading in programmable device configuration Feb. 4, 2014
8640062 Rapid estimation of temperature rise in wires due to Joule heating Jan. 28, 2014
8640066 Multi-phase models for timing closure of integrated circuit designs Jan. 28, 2014
8635579 Local clock skew optimization Jan. 21, 2014
8631365 Memory building blocks and memory design using automatic design tools Jan. 14, 2014
8631364 Constraining VLSI circuits Jan. 14, 2014
8627249 Method and system for generating design constraints Jan. 7, 2014
8627250 Method and system for high speed and low memory footprint static timing analysis Jan. 7, 2014
8627262 Automatic generation of merged mode constraints for electronic circuits Jan. 7, 2014
8621405 Incremental elmore delay calculation Dec. 31, 2013
8615725 Methods for compact modeling of circuit stages for static timing analysis of integrated circuit designs Dec. 24, 2013
8612910 Clock alias for timing analysis of an integrated circuit design Dec. 17, 2013
8612911 Estimating power consumption of an electronic circuit Dec. 17, 2013
8612913 Automated approach to planning critical signals and busses Dec. 17, 2013
8612922 Generalized constraint collection management method Dec. 17, 2013
8607186 Automatic verification of merged mode constraints for electronic circuits Dec. 10, 2013
8607176 Delay model construction in the presence of multiple input switching events Dec. 10, 2013
8601413 High-level synthesis device, high-level synthesis method, high-level synthesis program, and integrated circuit design method Dec. 3, 2013
8601420 Equivalent waveform model for static timing analysis of integrated circuit designs Dec. 3, 2013
8593177 Integrated circuit with timing aware clock-tree and method for designing such an integrated circuit Nov. 26, 2013

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