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Class Information
Number: 716/10
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Floorplanning > Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance)
Description: Subject matter wherein the arrangement of circuit block units or circuit components must satisfy one or more positional assignment restraints.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7624366 |
Clock aware placement |
Nov. 24, 2009 |
| 7620926 |
Methods and structures for flexible power management in integrated circuits |
Nov. 17, 2009 |
| 7620922 |
Method and system for optimized circuit autorouting |
Nov. 17, 2009 |
| 7620857 |
Controllable delay device |
Nov. 17, 2009 |
| 7617465 |
Method and mechanism for performing latch-up check on an IC design |
Nov. 10, 2009 |
| 7614141 |
Fabricating substrates having low inductance via arrangements |
Nov. 10, 2009 |
| 7614028 |
Representation, configuration, and reconfiguration of routing method and system |
Nov. 3, 2009 |
| 7614025 |
Method of placement for iterative implementation flows |
Nov. 3, 2009 |
| 7614024 |
Method to implement metal fill during integrated circuit design and layout |
Nov. 3, 2009 |
| 7610568 |
Methods and apparatus for making placement sensitive logic modifications |
Oct. 27, 2009 |
| 7607113 |
Wiring pattern determination method and computer program product thereof |
Oct. 20, 2009 |
| 7603643 |
Method and system for conducting design explorations of an integrated circuit |
Oct. 13, 2009 |
| 7603642 |
Placer with wires for RF and analog design |
Oct. 13, 2009 |
| 7603640 |
Multilevel IC floorplanner |
Oct. 13, 2009 |
| 7600208 |
Automatic placement of decoupling capacitors |
Oct. 6, 2009 |
| 7600207 |
Stress-managed revision of integrated circuit layouts |
Oct. 6, 2009 |
| 7600205 |
Net/wiring selection method, net selection method, wiring selection method, and delay improvement method |
Oct. 6, 2009 |
| 7596773 |
Automating optimal placement of macro-blocks in the design of an integrated circuit |
Sep. 29, 2009 |
| 7594214 |
Maximum flow analysis for electronic circuit design |
Sep. 22, 2009 |
| 7594213 |
Method and apparatus for computing dummy feature density for chemical-mechanical polishing |
Sep. 22, 2009 |
| 7594197 |
Semiconductor device having predictable electrical properties |
Sep. 22, 2009 |
| 7590962 |
Design method and architecture for power gate switch placement |
Sep. 15, 2009 |
| 7590961 |
Integrated circuit with signal skew adjusting cell selected from cell library |
Sep. 15, 2009 |
| 7590960 |
Placing partitioned circuit designs within iterative implementation flows |
Sep. 15, 2009 |
| 7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid |
Sep. 15, 2009 |
| 7587695 |
Protection boundaries in a parallel printed circuit board design environment |
Sep. 8, 2009 |
| 7587694 |
System and method for utilizing meta-cells |
Sep. 8, 2009 |
| 7587693 |
Apparatus and method of delay calculation for structured ASIC |
Sep. 8, 2009 |
| 7584447 |
PLD architecture for flexible placement of IP function blocks |
Sep. 1, 2009 |
| 7584446 |
Method and apparatus for extending processing time in one pipeline stage |
Sep. 1, 2009 |
| 7584445 |
Sequence-pair creating apparatus and sequence-pair creating method |
Sep. 1, 2009 |
| 7581198 |
Method and system for the modular design and layout of integrated circuits |
Aug. 25, 2009 |
| 7581197 |
Relative positioning of circuit elements in circuit design |
Aug. 25, 2009 |
| 7577933 |
Timing driven pin assignment |
Aug. 18, 2009 |
| 7571419 |
Methods and systems for performing design checking using a template |
Aug. 4, 2009 |
| 7571415 |
Layout of power device |
Aug. 4, 2009 |
| 7571410 |
Resonant tree driven clock distribution grid |
Aug. 4, 2009 |
| 7571409 |
Circuit design device and circuit design program |
Aug. 4, 2009 |
| 7571408 |
Methods and apparatus for diagonal route shielding |
Aug. 4, 2009 |
| 7568177 |
System and method for power gating of an integrated circuit |
Jul. 28, 2009 |
| 7565637 |
Method of designing package for semiconductor device, layout design tool for performing the same, and method of manufacturing semiconductor device using the same |
Jul. 21, 2009 |
| 7562327 |
Mask layout design improvement in gate width direction |
Jul. 14, 2009 |
| 7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a substrate |
Jul. 14, 2009 |
| 7555738 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Jun. 30, 2009 |
| 7555737 |
Auxiliary method for circuit design |
Jun. 30, 2009 |
| 7552414 |
Layout design apparatus, layout design method, and computer product |
Jun. 23, 2009 |
| 7552404 |
Semiconductor integrated device and apparatus for designing the same |
Jun. 23, 2009 |
| 7549142 |
Method and device for checking lithography data |
Jun. 16, 2009 |
| 7549137 |
Latch placement for high performance and low power circuits |
Jun. 16, 2009 |
| 7546567 |
Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip |
Jun. 9, 2009 |
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