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Class Information
Number: 716/10
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design > Floorplanning > Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance)
Description: Subject matter wherein the arrangement of circuit block units or circuit components must satisfy one or more positional assignment restraints.










Patents under this class:

Patent Number Title Of Patent Date Issued
7805697 Rotary clock synchronous fabric Sep. 28, 2010
7805694 Apparatus and method to facilitate hierarchical netlist checking Sep. 28, 2010
7802222 Generalized constraint collection management method Sep. 21, 2010
7802220 Method for effective placement of on-chip decoupling capacitors determined by maximum effective radii Sep. 21, 2010
7802219 Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout Sep. 21, 2010
7802218 Layout analysis method and apparatus for semiconductor integrated circuit Sep. 21, 2010
7797661 Method and apparatus for describing and managing properties of a transformer coil Sep. 14, 2010
7797660 Semiconductor integrated circuit for controlling substrate bias Sep. 14, 2010
7797655 Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage Sep. 14, 2010
7793247 Method and apparatus for directed physical implementation of a circuit design for an integrated circuit Sep. 7, 2010
7793246 Method for forming matching table of inner pads and outer pads and method for matching inner pads with outer pads using the same Sep. 7, 2010
7793245 Statistical iterative timing analysis of circuits having latches and/or feedback loops Sep. 7, 2010
7792663 Circuit simulation method Sep. 7, 2010
7788624 Methods of balancing logic resource usage in a programmable logic device Aug. 31, 2010
7788620 Input/output placement systems and methods to reduce simultaneous switching output noise Aug. 31, 2010
7788619 Memories, memory compiling systems and methods for the same Aug. 31, 2010
7788612 System, method, and computer program product for matching cell layout of an integrated circuit design Aug. 31, 2010
7788608 Microbump function assignment in a buck converter Aug. 31, 2010
7783998 Method and system for prototyping electronic devices with multi-configuration CHIP carriers Aug. 24, 2010
7779375 Design structure for shutting off data capture across asynchronous clock domains during at-speed testing Aug. 17, 2010
7774733 Method and apparatus for user interface in home network and electronic device and storage medium therefor Aug. 10, 2010
7774732 Method for radiation tolerance by automated placement Aug. 10, 2010
7774726 Dummy fill for integrated circuits Aug. 10, 2010
7765511 Compensation for performance variation in integrated circuits Jul. 27, 2010
7765508 Method and system for generating multiple implementation views of an IC design Jul. 27, 2010
7765506 Method and apparatus for automated synthesis of multi-channel circuits Jul. 27, 2010
7765505 Design rule management method, design rule management program, rule management apparatus and rule verification apparatus Jul. 27, 2010
7765504 Design method and system for minimizing blind via current loops Jul. 27, 2010
7761835 Semiconductor device design method, semiconductor device design system, and computer program for extracting parasitic parameters Jul. 20, 2010
7761833 Semiconductor device and dummy pattern arrangement method Jul. 20, 2010
7761832 Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model Jul. 20, 2010
7761831 ASIC design using clock and power grid standard cell Jul. 20, 2010
7761830 Method and system for providing placement based configurations in integrated circuits Jul. 20, 2010
7761822 File information generating method, file information generating apparatus, and storage medium storing file information generation program Jul. 20, 2010
7761819 System and method of modification of integrated circuit mask layout Jul. 20, 2010
7761818 Obtaining a feasible integer solution in a hierarchical circuit layout optimization Jul. 20, 2010
7757195 Methods and systems for implementing dummy fill for integrated circuits Jul. 13, 2010
7757194 Method and system for generating implementation files from a high level specification Jul. 13, 2010
7752591 Board layout check apparatus and board layout check method for guard wiring Jul. 6, 2010
7752588 Timing driven force directed placement flow Jul. 6, 2010
7752587 Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages Jul. 6, 2010
7752584 Method for verifying mask pattern of semiconductor device Jul. 6, 2010
7747975 Timing violation debugging inside place and route tool Jun. 29, 2010
7747974 Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure Jun. 29, 2010
7743356 Method of disposing dummy pattern Jun. 22, 2010
7739644 Methods, systems, and computer program products for grid-morphing techniques in placement, floorplanning, and legalization Jun. 15, 2010
7739638 Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have Jun. 15, 2010
7739636 Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise Jun. 15, 2010
7739627 System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells Jun. 15, 2010
7735046 E-fuse and method Jun. 8, 2010











 
 
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