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Class Information
Number: 716/1
Name: Data processing: design and analysis of circuit or semiconductor mask > Circuit design
Description: Subject matter comprising means or steps for sketching or outlining of layout of circuit components.
Sub-classes under this class:
| Class Number |
Class Name |
Patents |
| 716/8 |
Floorplanning |
1,014 |
| 716/18 |
Logical circuit synthesizer |
1,377 |
| 716/2 |
Optimization (e.g., redundancy, compaction) |
1,530 |
| 716/7 |
Partitioning (e.g., function block, ordering constraint) |
684 |
| 716/17 |
Programmable integrated circuit (e.g., basic cell, standard cell, macrocell) |
867 |
| 716/12 |
Routing (e.g., routing map, netlisting) |
1,120 |
| 716/4 |
Testing or evaluating |
2,710 |
| 716/3 |
Translation (e.g., conversion, equivalence) |
746 |
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620928 |
Method and apparatus for synthesizing a hardware system from a software description |
Nov. 17, 2009 |
| 7620917 |
Methods and apparatuses for automated circuit design |
Nov. 17, 2009 |
| 7620863 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits |
Nov. 17, 2009 |
| 7620827 |
Methods and apparatus for cooling integrated circuits |
Nov. 17, 2009 |
| 7617471 |
Processor event interface for programmable integrated circuit based circuit designs |
Nov. 10, 2009 |
| 7617467 |
Electrostatic discharge device verification in an integrated circuit |
Nov. 10, 2009 |
| 7617264 |
Parallel remembered-set processing respecting popular-object detection |
Nov. 10, 2009 |
| 7614025 |
Method of placement for iterative implementation flows |
Nov. 3, 2009 |
| 7614022 |
Testing for bridge faults in the interconnect of programmable integrated circuits |
Nov. 3, 2009 |
| 7614021 |
Optimal amplifier performance selection method |
Nov. 3, 2009 |
| 7614020 |
Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems |
Nov. 3, 2009 |
| 7610572 |
Semiconductor integrated circuit device with independent power domains |
Oct. 27, 2009 |
| 7610569 |
Chip design verification apparatus and data communication method for the same |
Oct. 27, 2009 |
| 7607112 |
Method and apparatus for performing metalization in an integrated circuit process |
Oct. 20, 2009 |
| 7603647 |
Recognition of a state machine in high-level integrated circuit description language code |
Oct. 13, 2009 |
| 7603645 |
Calibration method of insulating washer in circuit board |
Oct. 13, 2009 |
| 7603639 |
Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry |
Oct. 13, 2009 |
| 7603638 |
Method and system for modeling statistical leakage-current distribution |
Oct. 13, 2009 |
| 7603635 |
Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same |
Oct. 13, 2009 |
| 7603634 |
Various methods and apparatuses to preserve a logic state for a volatile latch circuit |
Oct. 13, 2009 |
| 7603579 |
Semiconductor chip and semiconductor integrated circuit device for relaying a reference clock from one hard macro to another |
Oct. 13, 2009 |
| 7600211 |
Toggle equivalence preserving logic synthesis |
Oct. 6, 2009 |
| 7600204 |
Method for simulation of negative bias and temperature instability |
Oct. 6, 2009 |
| 7600202 |
Techniques for providing a failures in time (FIT) rate for a product design process |
Oct. 6, 2009 |
| RE40925 |
Methods for automatically pipelining loops |
Sep. 29, 2009 |
| 7596772 |
Methodology and system for setup/hold time characterization of analog IP |
Sep. 29, 2009 |
| 7596482 |
System and method to analyze and determine ampacity risks on PCB interconnections |
Sep. 29, 2009 |
| 7594211 |
Methods and apparatuses for reset conditioning in integrated circuits |
Sep. 22, 2009 |
| 7594198 |
Ultra fine pitch I/O design for microchips |
Sep. 22, 2009 |
| 7594197 |
Semiconductor device having predictable electrical properties |
Sep. 22, 2009 |
| 7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus |
Sep. 22, 2009 |
| 7594195 |
Multithreaded reachability |
Sep. 22, 2009 |
| 7590967 |
Structured ASIC with configurable die size and selectable embedded functions |
Sep. 15, 2009 |
| 7590963 |
Integrating multiple electronic design applications |
Sep. 15, 2009 |
| 7590955 |
Method and system for implementing layout, placement, and routing with merged shapes |
Sep. 15, 2009 |
| 7590952 |
Compact chip package macromodels for chip-package simulation |
Sep. 15, 2009 |
| 7590951 |
Plug-in component-based dependency management for partitions within an incremental implementation flow |
Sep. 15, 2009 |
| 7587693 |
Apparatus and method of delay calculation for structured ASIC |
Sep. 8, 2009 |
| 7587686 |
Clock gating in a structured ASIC |
Sep. 8, 2009 |
| 7584447 |
PLD architecture for flexible placement of IP function blocks |
Sep. 1, 2009 |
| 7584446 |
Method and apparatus for extending processing time in one pipeline stage |
Sep. 1, 2009 |
| 7584443 |
Clock domain conflict analysis for timing graphs |
Sep. 1, 2009 |
| 7584437 |
Assuring correct data entry to generate shells for a semiconductor platform |
Sep. 1, 2009 |
| 7581200 |
System and method for analyzing length differences in differential signal paths |
Aug. 25, 2009 |
| 7581198 |
Method and system for the modular design and layout of integrated circuits |
Aug. 25, 2009 |
| 7581197 |
Relative positioning of circuit elements in circuit design |
Aug. 25, 2009 |
| 7577932 |
Gate modeling for semiconductor fabrication process effects |
Aug. 18, 2009 |
| 7577927 |
IC design modeling allowing dimension-dependent rule checking |
Aug. 18, 2009 |
| 7577926 |
Security-sensitive semiconductor product, particularly a smart-card chip |
Aug. 18, 2009 |
| 7577558 |
System and method for providing compact mapping between dissimilar memory systems |
Aug. 18, 2009 |
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