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Class Information
Number: 716
Name: Data processing: design and analysis of circuit or semiconductor mask >
Description: GENERAL STATEMENT OF THE CLASS SUBJECT MATTER
| Class Number |
Class Name |
No. of Patents | | | Applications (364/400) | | | 716/1 |
Circuit design |
1727 | | 716/8 |
Floorplanning |
1012 | | 716/10 |
Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance) |
1146 | | 716/9 |
Detailed placement (i.e., iterative improvement) |
687 | | 716/11 |
Layout editor (e.g., updating) |
1014 | | 716/18 |
Logical circuit synthesizer |
1365 | | 716/2 |
Optimization (e.g., redundancy, compaction) |
1525 | | 716/7 |
Partitioning (e.g., function block, ordering constraint) |
684 | | 716/17 |
Programmable integrated circuit (e.g., basic cell, standard cell, macrocell) |
860 | | 716/12 |
Routing (e.g., routing map, netlisting) |
1117 | | 716/14 |
Detailed routing (e.g., channel routing, switch box routing) |
591 | | 716/13 |
Global routing (e.g., shortest path, dead space, or duplicate trace elimination) |
671 | | 716/15 |
Pcb wiring |
291 | | 716/16 |
Pla, pld, fpga, or mcm |
908 | | 716/4 |
Testing or evaluating |
2694 | | 716/5 |
Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width) |
2220 | | 716/6 |
Timing analysis (e.g., delay time, path delay, latch timing) |
1720 | | 716/3 |
Translation (e.g., conversion, equivalence) |
742 | | 716/19 |
Design of semiconductor mask |
1218 | | 716/20 |
Mesh generation |
369 | | 716/21 |
Pattern exposure |
932 | |
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