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Class Information
Number: 714/733
Name: Error detection/correction and fault detection/recovery > Pulse or data error handling > Digital logic testing > Built-in testing circuit (bilbo)
Description: Subject matter in which the digital logic testing equipment includes a selectively configurable shift register, structurally a part of the device being tested.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7409614 |
Method, system and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit |
Aug. 5, 2008 |
| 7406640 |
Method and apparatus for testing a ring of non-scan latches with logic built-in self-test |
Jul. 29, 2008 |
| 7406643 |
Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium |
Jul. 29, 2008 |
| 7406644 |
Monitoring a thermal processing system |
Jul. 29, 2008 |
| 7404125 |
Compilable memory structure and test methodology for both ASIC and foundry test environments |
Jul. 22, 2008 |
| 7401281 |
Remote BIST high speed test and redundancy calculation |
Jul. 15, 2008 |
| 7401277 |
Semiconductor integrated circuit and scan test method therefor |
Jul. 15, 2008 |
| 7401271 |
Testing system and method of using same |
Jul. 15, 2008 |
| 7397263 |
Sensor differentiated fault isolation |
Jul. 8, 2008 |
| 7398443 |
Automatic fault-testing of logic blocks using internal at-speed logic-BIST |
Jul. 8, 2008 |
| 7395475 |
Circuit and method for fuse disposing in a semiconductor memory device |
Jul. 1, 2008 |
| 7395474 |
Lab-on-chip system and method and apparatus for manufacturing and operating same |
Jul. 1, 2008 |
| 7395466 |
Method and apparatus to adjust voltage for storage location reliability |
Jul. 1, 2008 |
| 7389460 |
Runtime-competitive fault handling for reconfigurable logic devices |
Jun. 17, 2008 |
| 7389459 |
Provision of debug via a separate ring bus in a data processing apparatus |
Jun. 17, 2008 |
| 7389458 |
Method and apparatus for the memory self-test of embedded memories in semiconductor chips |
Jun. 17, 2008 |
| 7389455 |
Register file initialization to prevent unknown outputs during test |
Jun. 17, 2008 |
| 7389454 |
Error detection in user input device using general purpose input-output |
Jun. 17, 2008 |
| 7386776 |
System for testing digital components |
Jun. 10, 2008 |
| 7382148 |
System and method for testing an LED and a connector thereof |
Jun. 3, 2008 |
| 7383481 |
Method and apparatus for testing a functional circuit at speed |
Jun. 3, 2008 |
| 7380190 |
RFID tag with bist circuits |
May. 27, 2008 |
| 7380180 |
Method, system, and apparatus for tracking defective cache lines |
May. 27, 2008 |
| 7380152 |
Daisy chained multi-device system and operating method |
May. 27, 2008 |
| 7380191 |
ABIST data compression and serialization for memory built-in self test of SRAM with redundancy |
May. 27, 2008 |
| 7375540 |
Process monitor for monitoring and compensating circuit performance |
May. 20, 2008 |
| 7376875 |
Method of improving logical built-in self test (LBIST) AC fault isolations |
May. 20, 2008 |
| 7376889 |
Memory device capable of detecting its failure |
May. 20, 2008 |
| 7373574 |
Semiconductor testing apparatus and method of testing semiconductor |
May. 13, 2008 |
| 7373573 |
Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing |
May. 13, 2008 |
| 7373569 |
Pulsed flop with scan circuitry |
May. 13, 2008 |
| 7368931 |
On-chip self test circuit and self test method for signal distortion |
May. 6, 2008 |
| 7370249 |
Method and apparatus for testing a memory array |
May. 6, 2008 |
| 7370254 |
Compressing test responses using a compactor |
May. 6, 2008 |
| 7370257 |
Test vehicle data analysis |
May. 6, 2008 |
| 7366953 |
Self test method and apparatus for identifying partially defective memory |
Apr. 29, 2008 |
| 7363563 |
Systems and methods for a built in test circuit for asynchronous testing of high-speed transceivers |
Apr. 22, 2008 |
| 7359820 |
In-cycle system test adaptation |
Apr. 15, 2008 |
| 7360134 |
Centralized BIST engine for testing on-chip memory structures |
Apr. 15, 2008 |
| 7360135 |
Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance |
Apr. 15, 2008 |
| 7356741 |
Modular test controller with BIST circuit for testing embedded DRAM circuits |
Apr. 8, 2008 |
| 7356746 |
Embedded testing circuit for testing a dual port memory |
Apr. 8, 2008 |
| 7356743 |
RRAM controller built in self test memory |
Apr. 8, 2008 |
| 7353162 |
Scalable reconfigurable prototyping system and method |
Apr. 1, 2008 |
| 7353442 |
On-chip and at-speed tester for testing and characterization of different types of memories |
Apr. 1, 2008 |
| 7353474 |
System and method for accessing signals of a user design in a programmable logic device |
Apr. 1, 2008 |
| 7350124 |
Method and apparatus for accelerating through-the pins LBIST simulation |
Mar. 25, 2008 |
| 7346824 |
Match circuit for performing pattern recognition in a performance counter |
Mar. 18, 2008 |
| 7346823 |
Automatic built-in self-test of logic with seeding from on-chip memory |
Mar. 18, 2008 |
| 7346822 |
Integrated circuit |
Mar. 18, 2008 |
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