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Class Information
Number: 714/731
Name: Error detection/correction and fault detection/recovery > Pulse or data error handling > Digital logic testing > Scan path testing (e.g., level sensitive scan design (lssd)) > Clock or synchronization
Description: Subject matter including a reference timing function or a clock-pulse generator for causing the various parts of the device to operate on a common time base.










Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14

Patent Number Title Of Patent Date Issued
8707117 Methods and apparatus to test multi clock domain data paths with a shared capture clock signal Apr. 22, 2014
8707118 Data, mode and ready bit packets on bidirectional control/data leads Apr. 22, 2014
8688404 Method and apparatus of common time-stamping Apr. 1, 2014
8689067 Control of clock gate cells during scan testing Apr. 1, 2014
8671320 Integrated circuit comprising scan test circuitry with controllable number of capture pulses Mar. 11, 2014
8667346 Semiconductor integrated circuit device, method of controlling the semiconductor integrated circuit device and information processing system Mar. 4, 2014
8666007 Methods and apparatus for synchronizing communication with a memory controller Mar. 4, 2014
8656238 Flip-flop circuit and scan flip-flop circuit Feb. 18, 2014
8633722 Method and circuit for testing accuracy of delay circuitry Jan. 21, 2014
8635040 Signal measuring device and signal measuring method Jan. 21, 2014
8631290 Automated detection of and compensation for guardband degradation during operation of clocked data processing circuit Jan. 14, 2014
8631293 Trace circuitry connected to TAP domain and address-command port Jan. 14, 2014
8631291 Semiconductor device and test method with boundary scan Jan. 14, 2014
8627161 Low power divided scan paths with adapter and scan controller Jan. 7, 2014
8621303 Clock control circuitry and methods of utilizing the clock control circuitry Dec. 31, 2013
8621300 State machine moving from test control register update to idle Dec. 31, 2013
8621299 IR outputting mode-1 and ATC enable; ATC gating of update-1 Dec. 31, 2013
8607108 Scan testing with capture clock generator driven by clock distribution network Dec. 10, 2013
8595681 Method and apparatus to use physical design information to detect IR drop prone test patterns Nov. 26, 2013
8595554 Reproducibility in a multiprocessor system Nov. 26, 2013
8595575 Semiconductor memory device, test circuit, and test operation method thereof Nov. 26, 2013
8589746 Bidirectional clock, data, and control to functional and test circuitry Nov. 19, 2013
8578226 Apparatus and system for implementing variable speed scan testing Nov. 5, 2013
8572543 Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage Oct. 29, 2013
8560903 System and method for executing functional scanning in an integrated circuit environment Oct. 15, 2013
8555121 Pulse dynamic logic gates with LSSD scan functionality Oct. 8, 2013
8555124 Apparatus and method for detecting an approaching error condition Oct. 8, 2013
8543966 Test path selection and test program generation for performance testing integrated circuit chips Sep. 24, 2013
8533547 Continuous application and decompression of test patterns and selective compaction of test responses Sep. 10, 2013
8533548 Wrapper cell for hierarchical system on chip testing Sep. 10, 2013
8531208 Flip-flop and semiconductor device including the same Sep. 10, 2013
8522096 Method and apparatus for testing 3D integrated circuits Aug. 27, 2013
8516318 Dynamic scan Aug. 20, 2013
8516316 Method and apparatus for diagnosing an integrated circuit Aug. 20, 2013
8510616 Scalable scan-based test architecture with reduced test time and test power Aug. 13, 2013
8499230 Critical path monitor for an integrated circuit and method of operation thereof Jul. 30, 2013
8489947 Circuit and method for simultaneously measuring multiple changes in delay Jul. 16, 2013
8484523 Sequential digital circuitry with test scan Jul. 9, 2013
8479068 Decoded register outputs enabling test clock to selected asynchronous domains Jul. 2, 2013
8473795 IC with wrapper, TAM, TAM controller, and DDR circuitry Jun. 25, 2013
8473794 First, update, and second TDI and TMS flip-flop TAP circuitry Jun. 25, 2013
8468404 Method and system for reducing switching activity during scan-load operations Jun. 18, 2013
8468407 Method for creating test clock domain during integrated circuit design, and associated computer readable medium Jun. 18, 2013
8468409 Speed-path debug using at-speed scan test patterns Jun. 18, 2013
8464113 Scan architecture for full custom blocks with improved scan latch Jun. 11, 2013
8464117 System for testing integrated circuit with asynchronous clock domains Jun. 11, 2013
8458544 Multiple-capture DFT system to reduce peak capture power during self-test or scan test Jun. 4, 2013
8458543 Scan based test architecture and method Jun. 4, 2013
8458542 Analog scan circuit, analog flip-flop, and data processing apparatus Jun. 4, 2013
8443246 Control of clock gate cells during scan testing May. 14, 2013

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