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Class Information
Number: 714/726
Name: Error detection/correction and fault detection/recovery > Pulse or data error handling > Digital logic testing > Scan path testing (e.g., level sensitive scan design (lssd))
Description: Subject matter in which digital logic is designed for improved testability by including shift register latches (SRL) to enable the configuring of the circuitry into combinational logic form.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7627798 |
Systems and methods for circuit testing using LBIST |
Dec. 1, 2009 |
| 7627797 |
Test access port |
Dec. 1, 2009 |
| 7620865 |
Scan string segmentation for digital test compression |
Nov. 17, 2009 |
| 7620864 |
Method and apparatus for controlling access to and/or exit from a portion of scan chain |
Nov. 17, 2009 |
| 7617431 |
Method and apparatus for analyzing delay defect |
Nov. 10, 2009 |
| 7617429 |
Automatable scan partitioning for low power using external control |
Nov. 10, 2009 |
| 7617425 |
Method for at-speed testing of memory interface using scan |
Nov. 10, 2009 |
| 7613972 |
Semiconductor integrated circuit, and designing method and testing method thereof |
Nov. 3, 2009 |
| 7613971 |
Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit |
Nov. 3, 2009 |
| 7613969 |
Method and system for clock skew independent scan register chains |
Nov. 3, 2009 |
| 7613967 |
Inversion of scan clock for scan cells |
Nov. 3, 2009 |
| 7610534 |
Determining a length of the instruction register of an unidentified device on a scan chain |
Oct. 27, 2009 |
| 7610533 |
Semiconductor integrated circuit and method for testing the same |
Oct. 27, 2009 |
| 7610531 |
Modifying a test pattern to control power supply noise |
Oct. 27, 2009 |
| 7607059 |
Systems and methods for improved scan testing fault coverage |
Oct. 20, 2009 |
| 7607056 |
Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices |
Oct. 20, 2009 |
| 7600167 |
Flip-flop, shift register, and scan test circuit |
Oct. 6, 2009 |
| 7600166 |
Method and system for providing trusted access to a JTAG scan interface in a microprocessor |
Oct. 6, 2009 |
| 7596737 |
System and method for testing state retention circuits |
Sep. 29, 2009 |
| 7596734 |
On-Chip AC self-test controller |
Sep. 29, 2009 |
| 7596733 |
Dynamically reconfigurable shared scan-in test architecture |
Sep. 29, 2009 |
| 7596732 |
Digital storage element architecture comprising dual scan clocks and gated scan output |
Sep. 29, 2009 |
| 7594150 |
Fault-tolerant architecture of flip-flops for transient pulses and signal delays |
Sep. 22, 2009 |
| 7594149 |
In-situ monitor of process and device parameters in integrated circuits |
Sep. 22, 2009 |
| 7590908 |
Semiconductor integrated circuit and method for testing the same |
Sep. 15, 2009 |
| 7590907 |
Method and apparatus for soft-error immune and self-correcting latches |
Sep. 15, 2009 |
| 7590906 |
Scan flip-flop circuit and semiconductor integrated circuit device |
Sep. 15, 2009 |
| 7590905 |
Method and apparatus for pipelined scan compression |
Sep. 15, 2009 |
| 7587643 |
System and method of integrated circuit testing |
Sep. 8, 2009 |
| 7584393 |
Scan test circuit and method of arranging the same |
Sep. 1, 2009 |
| 7584392 |
Test compaction using linear-matrix driven scan chains |
Sep. 1, 2009 |
| 7581150 |
Methods and computer program products for debugging clock-related scan testing failures of integrated circuits |
Aug. 25, 2009 |
| 7581149 |
Scan chain extracting method, test apparatus, circuit device, and scan chain extracting program |
Aug. 25, 2009 |
| 7577887 |
JTAG interface device of mobile terminal and method thereof |
Aug. 18, 2009 |
| 7574644 |
Functional pattern logic diagnostic method |
Aug. 11, 2009 |
| 7574642 |
Multiple uses for BIST test latches |
Aug. 11, 2009 |
| 7574640 |
Compacting circuit responses |
Aug. 11, 2009 |
| 7574638 |
Semiconductor device tested using minimum pins and methods of testing the same |
Aug. 11, 2009 |
| 7571402 |
Scan chain modification for reduced leakage |
Aug. 4, 2009 |
| 7571364 |
Selectable JTAG or trace access with data store and output |
Aug. 4, 2009 |
| 7570076 |
Segmented programmable capacitor array for improved density and reduced leakage |
Aug. 4, 2009 |
| 7568141 |
Method and apparatus for testing embedded cores |
Jul. 28, 2009 |
| 7568140 |
Integrated circuit having configurable cells and a secured test mode |
Jul. 28, 2009 |
| 7568139 |
Process for identifying the location of a break in a scan chain in real time |
Jul. 28, 2009 |
| 7568138 |
Method to prevent firmware defects from disturbing logic clocks to improve system reliability |
Jul. 28, 2009 |
| 7565591 |
Testing of circuits with multiple clock domains |
Jul. 21, 2009 |
| 7565588 |
Semiconductor device and data storage apparatus |
Jul. 21, 2009 |
| 7562276 |
Apparatus and method for testing and debugging an integrated circuit |
Jul. 14, 2009 |
| 7562275 |
Tri-level test mode terminal in limited terminal environment |
Jul. 14, 2009 |
| 7562274 |
User data driven test control software application the requires no software maintenance |
Jul. 14, 2009 |
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