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Class Information
Number: 714/726
Name: Error detection/correction and fault detection/recovery > Pulse or data error handling > Digital logic testing > Scan path testing (e.g., level sensitive scan design (lssd))
Description: Subject matter in which digital logic is designed for improved testability by including shift register latches (SRL) to enable the configuring of the circuitry into combinational logic form.










Sub-classes under this class:

Class Number Class Name Patents
714/730 Addressing 102
714/727 Boundary scan 994
714/731 Clock or synchronization 694
714/729 Plural scan paths 727
714/728 Random pattern generation (includes pseudorandom pattern) 241


Patents under this class:

Patent Number Title Of Patent Date Issued
8713386 Device for increasing chip testing efficiency and method thereof Apr. 29, 2014
8707118 Data, mode and ready bit packets on bidirectional control/data leads Apr. 22, 2014
8707116 Transitioning a state machine through idle, sequence, and unlock states Apr. 22, 2014
8707115 Micro controller, driving method thereof and display device using the same Apr. 22, 2014
8707114 Semiconductor device including a test circuit that generates test signals to be used for adjustment on operation of an internal circuit Apr. 22, 2014
8707113 Method for modeling a device and generating test for that device Apr. 22, 2014
8694951 Core wrapping in the presence of an embedded wrapped core Apr. 8, 2014
8694843 Clock control of pipelined memory for improved delay fault testing Apr. 8, 2014
8694842 Configurable Mux-D scan flip-flop design Apr. 8, 2014
8692248 Integrated circuit die having input and output circuit pads, test circuitry, and multiplex circuitry Apr. 8, 2014
8689070 Method and system for scan chain diagnosis Apr. 1, 2014
8689067 Control of clock gate cells during scan testing Apr. 1, 2014
8683280 Test generator for low power built-in self-test Mar. 25, 2014
8683278 Semiconductor device Mar. 25, 2014
8682501 Data processing device, microcontroller, and self-diagnosis method of data processing device Mar. 25, 2014
8677201 Semiconductor integrated circuit and method of retrieving signal to semiconductor integrated circuit Mar. 18, 2014
8677200 Integrated circuit with transition control circuitry for limiting scan test signal transitions during scan testing Mar. 18, 2014
8677199 Pulse dynamic logic gates with mux-D scan functionality Mar. 18, 2014
8677198 Method and apparatus for system testing using multiple processors Mar. 18, 2014
8671319 Dynamic device identification for making a JTAG debug connection with a internet browser Mar. 11, 2014
8671318 Core circuit including dual mode TAP and scan test port Mar. 11, 2014
8667349 Scan flip-flop circuit having fast setup time Mar. 4, 2014
8661304 Test pattern generation for diagnosing scan chain failures Feb. 25, 2014
8661303 Mechanism to instantiate a JTAG debugger in a browser Feb. 25, 2014
8661302 Enhanced debug/test capability to a core reset process Feb. 25, 2014
8656238 Flip-flop circuit and scan flip-flop circuit Feb. 18, 2014
8656236 Remote boundary scanning Feb. 18, 2014
8656234 Test port connected to master output of override selection logic Feb. 18, 2014
8656233 Scan cell designs with serial and parallel loading of test data Feb. 18, 2014
8650519 Automated functional coverage for an integrated circuit design Feb. 11, 2014
8645779 Scan testing of integrated circuits and on-chip modules Feb. 4, 2014
8645778 Scan test circuitry with delay defect bypass functionality Feb. 4, 2014
8639992 Soft error rate detector Jan. 28, 2014
8635504 Communications under active and inert state machine sequences Jan. 21, 2014
8635503 Scan latch with phase-free scan enable Jan. 21, 2014
8631289 Scan topology discovery in target systems Jan. 14, 2014
8627160 System and device for reducing instantaneous voltage droop during a scan shift operation Jan. 7, 2014
8621303 Clock control circuitry and methods of utilizing the clock control circuitry Dec. 31, 2013
8621299 IR outputting mode-1 and ATC enable; ATC gating of update-1 Dec. 31, 2013
8621297 Scan path switches selectively connecting input buffer and test leads Dec. 31, 2013
8621296 Integrated circuit devices having selectively enabled scan paths with power saving circuitry Dec. 31, 2013
8621295 Circuit module, semiconductor integrated circuit, and inspection apparatus and method thereof Dec. 31, 2013
8615695 Fault dictionary-based scan chain failure diagnosis Dec. 24, 2013
8615693 Scan test circuitry comprising scan cells with multiple scan inputs Dec. 24, 2013
8615692 Method and system for analyzing test vectors to determine toggle counts Dec. 24, 2013
8615691 Process for improving design-limited yield by localizing potential faults from production test data Dec. 24, 2013
8612809 Systems, methods, and apparatuses for stacked memory Dec. 17, 2013
8607337 Scanning circuit and method for data content Dec. 10, 2013
8607109 Test circuitry including core output, expected response, and mask circuitry Dec. 10, 2013
8604475 IC dies with serarate connections to expected and mask data Dec. 10, 2013











 
 
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