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Class Information
Number: 714/725
Name: Error detection/correction and fault detection/recovery > Pulse or data error handling > Digital logic testing > Programmable logic array (pla) testing
Description: Subject matter for testing an array of logical elements selectively configurable to sequentially perform various binary logic functions.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620853 |
Methods for detecting resistive bridging faults at configuration random-access memory output nodes |
Nov. 17, 2009 |
| 7620862 |
Method of and system for testing an integrated circuit |
Nov. 17, 2009 |
| 7620863 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits |
Nov. 17, 2009 |
| 7620876 |
Reducing false positives in configuration error detection for programmable devices |
Nov. 17, 2009 |
| 7620883 |
Techniques for mitigating, detecting, and correcting single event upset effects |
Nov. 17, 2009 |
| 7609087 |
Integrated circuit device programming with partial power |
Oct. 27, 2009 |
| 7603599 |
Method to test routed networks |
Oct. 13, 2009 |
| 7590903 |
Re-configurable architecture for automated test equipment |
Sep. 15, 2009 |
| 7590904 |
Systems and methods for detecting a failure event in a field programmable gate array |
Sep. 15, 2009 |
| 7580037 |
Techniques for graphical analysis and manipulation of circuit timing requirements |
Aug. 25, 2009 |
| 7577055 |
Error detection on programmable logic resources |
Aug. 18, 2009 |
| 7574533 |
Apparatus and methods for communicating with programmable logic devices |
Aug. 11, 2009 |
| 7571035 |
Simultaneous vehicle protocol communication apparatus and method |
Aug. 4, 2009 |
| 7571412 |
Method and system for semiconductor device characterization pattern generation and analysis |
Aug. 4, 2009 |
| 7568137 |
Method and apparatus for a clock and data recovery circuit |
Jul. 28, 2009 |
| 7568136 |
Reconfigurable system and method with corruption detection and recovery |
Jul. 28, 2009 |
| 7552370 |
Application specific distributed test engine architecture system and method |
Jun. 23, 2009 |
| 7546499 |
Communication signal testing with a programmable logic device |
Jun. 9, 2009 |
| 7539913 |
Systems and methods for chip testing |
May. 26, 2009 |
| 7539914 |
Method of refreshing configuration data in an integrated circuit |
May. 26, 2009 |
| 7536615 |
Logic analyzer systems and methods for programmable logic devices |
May. 19, 2009 |
| 7529993 |
Method of selectively programming integrated circuits to compensate for process variations and/or mask revisions |
May. 5, 2009 |
| 7529992 |
Configurable integrated circuit with error correcting circuitry |
May. 5, 2009 |
| 7529294 |
Testing of multiple asynchronous logic domains |
May. 5, 2009 |
| 7526694 |
Integrated circuit internal test circuit and method of testing therewith |
Apr. 28, 2009 |
| 7516375 |
Methods and systems for repairing an integrated circuit device |
Apr. 7, 2009 |
| 7512848 |
Clock and data recovery circuit having operating parameter compensation circuitry |
Mar. 31, 2009 |
| 7512849 |
Reconfigurable programmable logic system with configuration recovery mode |
Mar. 31, 2009 |
| 7512850 |
Checkpointing user design states in a configurable IC |
Mar. 31, 2009 |
| 7512871 |
Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays |
Mar. 31, 2009 |
| 7509547 |
System and method for testing of interconnects in a programmable logic device |
Mar. 24, 2009 |
| 7500162 |
Sourcing internal signals to output pins of an integrated circuit through sequential multiplexing |
Mar. 3, 2009 |
| 7496820 |
Method and apparatus for generating test vectors for an integrated circuit under test |
Feb. 24, 2009 |
| 7493543 |
Determining timing associated with an input or output of an embedded circuit in an integrated circuit for testing |
Feb. 17, 2009 |
| 7487571 |
Control adjustable device configurations to induce parameter variations to control parameter skews |
Feb. 10, 2009 |
| 7487416 |
Self test device and self test method for reconfigurable device mounted board |
Feb. 3, 2009 |
| 7487415 |
Memory circuitry with data validation |
Feb. 3, 2009 |
| 7480843 |
Configuration access from a boundary-scannable device |
Jan. 20, 2009 |
| 7480842 |
Method and apparatus for reducing the number of test designs for device testing |
Jan. 20, 2009 |
| 7480825 |
Method for debugging reconfigurable architectures |
Jan. 20, 2009 |
| 7475315 |
Configurable built in self test circuitry for testing memory arrays |
Jan. 6, 2009 |
| 7469371 |
Methods of testing a user design in a programmable integrated circuit |
Dec. 23, 2008 |
| 7444566 |
Memory device fail summary data reduction for improved redundancy analysis |
Oct. 28, 2008 |
| 7444565 |
Re-programmable COMSEC module |
Oct. 28, 2008 |
| 7437635 |
Testing hard-wired IP interface signals using a soft scan chain |
Oct. 14, 2008 |
| 7437633 |
Duty cycle characterization and adjustment |
Oct. 14, 2008 |
| 7430697 |
Method of testing circuit blocks of a programmable logic device |
Sep. 30, 2008 |
| 7426665 |
Tileable field-programmable gate array architecture |
Sep. 16, 2008 |
| 7424655 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits |
Sep. 9, 2008 |
| 7412635 |
Utilizing multiple bitstreams to avoid localized defects in partially defective programmable integrated circuits |
Aug. 12, 2008 |
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