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Class Information
Number: 714/724
Name: Error detection/correction and fault detection/recovery > Pulse or data error handling > Digital logic testing
Description: Subject matter in which the diagnostic test is performed upon a system or element performing a binary logic operation upon a signal having plural distinct discrete states.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6910164 |
High-resistance contact detection test mode |
Jun. 21, 2005 |
| 6903566 |
Semiconductor device tester |
Jun. 7, 2005 |
| 6897678 |
Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits |
May. 24, 2005 |
| 6898563 |
System for aiding in the design of combinatorial logic and sequential state machines |
May. 24, 2005 |
| 6898720 |
Scalable extensible network test architecture |
May. 24, 2005 |
| 6898745 |
Integrated device with operativity testing |
May. 24, 2005 |
| 6898746 |
Method of and apparatus for testing a serial differential/mixed signal device |
May. 24, 2005 |
| 6898747 |
Method for testing circuit units to be tested with increased data compression for burn-in |
May. 24, 2005 |
| 6898748 |
Test circuit method and apparatus |
May. 24, 2005 |
| 6893973 |
Method of etching silicon nitride film and method of producing semiconductor device |
May. 17, 2005 |
| 6894503 |
Preconditional quiescent current testing of a semiconductor device |
May. 17, 2005 |
| 6895536 |
Testable up down counter for use in a logic analyzer |
May. 17, 2005 |
| 6895539 |
Universal method and apparatus for controlling a functional test system |
May. 17, 2005 |
| 6895548 |
Semiconductor testing apparatus and method for optimizing a wait time until stabilization of semiconductor device output signal |
May. 17, 2005 |
| 6888366 |
Apparatus and method for testing a plurality of semiconductor chips |
May. 3, 2005 |
| 6889334 |
Multimode system for calibrating a data strobe delay for a memory read operation |
May. 3, 2005 |
| 6889348 |
Tester architecture construction data generating method, tester architecture constructing method and test circuit |
May. 3, 2005 |
| 6885952 |
System and method for determining voltage levels |
Apr. 26, 2005 |
| 6885961 |
Hybrid tester architecture |
Apr. 26, 2005 |
| 6885962 |
Signal inspection device |
Apr. 26, 2005 |
| 6886122 |
Method for testing integrated circuits with memory element access |
Apr. 26, 2005 |
| 6882620 |
Token exchange system with fault protection |
Apr. 19, 2005 |
| 6883134 |
Method and program product for detecting bus conflict and floating bus conditions in circuit designs |
Apr. 19, 2005 |
| 6880116 |
System for testing multiple devices on a single system and method thereof |
Apr. 12, 2005 |
| 6880137 |
Dynamically reconfigurable precision signal delay test system for automatic test equipment |
Apr. 12, 2005 |
| 6876207 |
System and method for testing devices |
Apr. 5, 2005 |
| 6871308 |
Semiconductor inspection method |
Mar. 22, 2005 |
| 6871309 |
Verification of redundant safety functions on a monolithic integrated circuit |
Mar. 22, 2005 |
| 6871310 |
Binary time-frame expansion of sequential systems |
Mar. 22, 2005 |
| 6868512 |
Fault detection system with real-time database |
Mar. 15, 2005 |
| 6868532 |
Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby |
Mar. 15, 2005 |
| 6864699 |
Apparatus for testing integrated circuits having an integrated unit for testing digital and analog signals |
Mar. 8, 2005 |
| 6865703 |
Scan test system for semiconductor device |
Mar. 8, 2005 |
| 6858447 |
Method for testing semiconductor chips |
Feb. 22, 2005 |
| 6857089 |
Differential receiver architecture |
Feb. 15, 2005 |
| 6857090 |
System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices |
Feb. 15, 2005 |
| 6857091 |
Method for operating a TAP controller and corresponding TAP controller |
Feb. 15, 2005 |
| 6851079 |
Jtag test access port controller used to control input/output pad functionality |
Feb. 1, 2005 |
| 6848049 |
Method and apparatus for the authentication of integrated circuits |
Jan. 25, 2005 |
| 6848066 |
Error reduction in semiconductor processes |
Jan. 25, 2005 |
| 6845345 |
System for monitoring and analyzing diagnostic data of spin tracks |
Jan. 18, 2005 |
| 6845477 |
Semiconductor test device for conducting an operation test in parallel on many chips in a wafer test and semiconductor test method |
Jan. 18, 2005 |
| 6839874 |
Method and apparatus for testing an embedded device |
Jan. 4, 2005 |
| 6836757 |
Emulation system employing serial test port and alternative data transfer protocol |
Dec. 28, 2004 |
| 6836864 |
Methods of testing a digital frequency synthesizer in a programmable logic device using a reduced set of multiplier and divider values |
Dec. 28, 2004 |
| 6829553 |
Method of and apparatus for measuring the correctness of and correcting an automatic test arrangement |
Dec. 7, 2004 |
| 6829730 |
Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same |
Dec. 7, 2004 |
| 6822474 |
On chip logic analyzer debug bus |
Nov. 23, 2004 |
| 6822482 |
Dynamic scan circuitry for B-phase |
Nov. 23, 2004 |
| 6823293 |
Hierarchical power supply noise monitoring device and system for very large scale integrated circuits |
Nov. 23, 2004 |
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