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Class Information
Number: 714/724
Name: Error detection/correction and fault detection/recovery > Pulse or data error handling > Digital logic testing
Description: Subject matter in which the diagnostic test is performed upon a system or element performing a binary logic operation upon a signal having plural distinct discrete states.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7404124 |
On-chip sampling circuit and method |
Jul. 22, 2008 |
| 7404123 |
Automated test and characterization data analysis methods and arrangement |
Jul. 22, 2008 |
| 7404122 |
Mapping logic for loading control of crossbar multiplexer select RAM |
Jul. 22, 2008 |
| 7404121 |
Method and machine-readable media for inferring relationships between test results |
Jul. 22, 2008 |
| 7404120 |
Verification of event handling |
Jul. 22, 2008 |
| 7404119 |
Circuit for testing power down reset function of an electronic device |
Jul. 22, 2008 |
| 7404115 |
Self-synchronising bit error analyser and circuit |
Jul. 22, 2008 |
| 7404114 |
System and method for balancing delay of signal communication paths through well voltage adjustment |
Jul. 22, 2008 |
| 7401276 |
Semiconductor device with test circuit and test method of the same |
Jul. 15, 2008 |
| 7401275 |
Automated test and characterization web services |
Jul. 15, 2008 |
| 7401274 |
Method of performing programming and diagnostic functions for a microcontroller |
Jul. 15, 2008 |
| 7401273 |
Recovery from errors in a data processing apparatus |
Jul. 15, 2008 |
| 7401272 |
Apparatus and method for high speed sampling or testing of data signals using automated testing equipment |
Jul. 15, 2008 |
| 7398445 |
Method and system for debug and test using replicated logic |
Jul. 8, 2008 |
| 7398440 |
Tap multiplexer |
Jul. 8, 2008 |
| 7398181 |
Method for retrieving reliability data in a system |
Jul. 8, 2008 |
| 7395475 |
Circuit and method for fuse disposing in a semiconductor memory device |
Jul. 1, 2008 |
| 7395467 |
Remove signal from TAP selection circuitry to multiplexer control circuitry |
Jul. 1, 2008 |
| 7395466 |
Method and apparatus to adjust voltage for storage location reliability |
Jul. 1, 2008 |
| 7395169 |
Memory test engine |
Jul. 1, 2008 |
| 7392445 |
Autonomic bus reconfiguration for fault conditions |
Jun. 24, 2008 |
| 7389455 |
Register file initialization to prevent unknown outputs during test |
Jun. 17, 2008 |
| 7389453 |
Queuing methods for distributing programs for producing test data |
Jun. 17, 2008 |
| 7389452 |
Methods and apparatus for monitoring internal signals in an integrated circuit |
Jun. 17, 2008 |
| 7389215 |
Efficient presentation of functional coverage results |
Jun. 17, 2008 |
| 7386773 |
Method and system for testing distributed logic circuitry |
Jun. 10, 2008 |
| 7386772 |
Test module for testing of electronic systems |
Jun. 10, 2008 |
| 7383481 |
Method and apparatus for testing a functional circuit at speed |
Jun. 3, 2008 |
| 7383478 |
Wireless dynamic boundary-scan topologies for field |
Jun. 3, 2008 |
| 7383477 |
Interface circuit for using a low voltage logic tester to test a high voltage IC |
Jun. 3, 2008 |
| 7383367 |
Progressive extended compression mask for dynamic trace |
Jun. 3, 2008 |
| 7380184 |
Sequential scan technique providing enhanced fault coverage in an integrated circuit |
May. 27, 2008 |
| 7380182 |
Method and apparatus for checking output signals of an integrated circuit |
May. 27, 2008 |
| 7380181 |
Test circuit and method for hierarchical core |
May. 27, 2008 |
| 7379395 |
Precise time measurement apparatus and method |
May. 27, 2008 |
| 7376917 |
Client-server semiconductor verification system |
May. 20, 2008 |
| 7376874 |
Method of controlling a test mode of a circuit |
May. 20, 2008 |
| 7376873 |
Method and system for selectively masking test responses |
May. 20, 2008 |
| 7376872 |
Testing embedded memory in integrated circuits such as programmable logic devices |
May. 20, 2008 |
| 7373623 |
Method and apparatus for locating circuit deviations |
May. 13, 2008 |
| 7373574 |
Semiconductor testing apparatus and method of testing semiconductor |
May. 13, 2008 |
| 7373572 |
System pulse latch and shadow pulse latch coupled to output joining circuit |
May. 13, 2008 |
| 7373570 |
LSI device having scan separators provided in number reduced from signal lines of combinatorial circuits |
May. 13, 2008 |
| 7373566 |
Semiconductor device for accurate measurement of time parameters in operation |
May. 13, 2008 |
| 7373565 |
Start/stop circuit for performance counter |
May. 13, 2008 |
| 7370257 |
Test vehicle data analysis |
May. 6, 2008 |
| 7370253 |
Apparatus and method for high-speed SAS link protocol testing |
May. 6, 2008 |
| 7370247 |
Dynamic offset compensation based on false transitions |
May. 6, 2008 |
| RE40282 |
Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device |
Apr. 29, 2008 |
| 7366967 |
Methods of testing semiconductor memory devices in a variable CAS latency environment and related semiconductor test devices |
Apr. 29, 2008 |
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