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Class Information
Number: 714/715
Name: Error detection/correction and fault detection/recovery > Pulse or data error handling > Transmission facility testing > Test pattern with comparison
Description: Subject matter in which the transmission facility is tested by applying a test pattern to the device under test and comparing the output to a reference test pattern.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620861 |
Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels |
Nov. 17, 2009 |
| 7617426 |
Verification method and apparatus |
Nov. 10, 2009 |
| 7613974 |
Fault detection method and apparatus |
Nov. 3, 2009 |
| 7610526 |
On-chip circuitry for bus validation |
Oct. 27, 2009 |
| 7610522 |
Compliance of master-slave modes for low-level debug of serial links |
Oct. 27, 2009 |
| 7603596 |
Memory device capable of detecting its failure |
Oct. 13, 2009 |
| 7600162 |
Semiconductor device |
Oct. 6, 2009 |
| 7599301 |
Communications network tap with heartbeat monitor |
Oct. 6, 2009 |
| 7587645 |
Input circuit of semiconductor memory device and test system having the same |
Sep. 8, 2009 |
| 7574633 |
Test apparatus, adjustment method and recording medium |
Aug. 11, 2009 |
| 7571365 |
Wafer scale testing using a 2 signal JTAG interface |
Aug. 4, 2009 |
| 7559001 |
Method and apparatus for executing commands and generation of automation scripts and test cases |
Jul. 7, 2009 |
| 7549101 |
Clock transferring apparatus, and testing apparatus |
Jun. 16, 2009 |
| 7539148 |
Circuit integrity in a packet-switched network |
May. 26, 2009 |
| 7512854 |
Method and apparatus for testing, characterizing and monitoring a chip interface using a second data path |
Mar. 31, 2009 |
| 7506222 |
System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling |
Mar. 17, 2009 |
| 7506311 |
Test tool for application programming interfaces |
Mar. 17, 2009 |
| 7500046 |
Abstracted host bus interface for complex high performance ASICs |
Mar. 3, 2009 |
| 7493532 |
Methods and structure for optimizing SAS domain link quality and performance |
Feb. 17, 2009 |
| 7490275 |
Method and apparatus for evaluating and optimizing a signaling system |
Feb. 10, 2009 |
| 7487423 |
Decoding method, medium, and apparatus |
Feb. 3, 2009 |
| 7480839 |
Qualified anomaly detection |
Jan. 20, 2009 |
| 7478298 |
Method and system for backplane testing using generic boundary-scan units |
Jan. 13, 2009 |
| 7478304 |
Apparatus for accelerating through-the-pins LBIST simulation |
Jan. 13, 2009 |
| 7461308 |
Method for testing semiconductor chips by means of bit masks |
Dec. 2, 2008 |
| 7454676 |
Method for testing semiconductor chips using register sets |
Nov. 18, 2008 |
| 7447966 |
Hardware verification scripting |
Nov. 4, 2008 |
| 7447953 |
Lane testing with variable mapping |
Nov. 4, 2008 |
| 7444558 |
Programmable measurement mode for a serial point to point link |
Oct. 28, 2008 |
| 7437643 |
Automated BIST execution scheme for a link |
Oct. 14, 2008 |
| 7434114 |
Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same |
Oct. 7, 2008 |
| 7434118 |
Parameterized signal conditioning |
Oct. 7, 2008 |
| 7426599 |
Systems and methods for writing data with a FIFO interface |
Sep. 16, 2008 |
| 7405723 |
Apparatus for testing display device and method for testing the same |
Jul. 29, 2008 |
| 7404115 |
Self-synchronising bit error analyser and circuit |
Jul. 22, 2008 |
| 7404114 |
System and method for balancing delay of signal communication paths through well voltage adjustment |
Jul. 22, 2008 |
| 7395466 |
Method and apparatus to adjust voltage for storage location reliability |
Jul. 1, 2008 |
| 7386767 |
Programmable bit error rate monitor for serial interface |
Jun. 10, 2008 |
| 7380152 |
Daisy chained multi-device system and operating method |
May. 27, 2008 |
| 7373561 |
Integrated packet bit error rate tester for 10G SERDES |
May. 13, 2008 |
| 7360127 |
Method and apparatus for evaluating and optimizing a signaling system |
Apr. 15, 2008 |
| 7349506 |
Semiconductor integrated circuit and method for testing the same |
Mar. 25, 2008 |
| 7340655 |
Skew adjustment circuit, skew adjustment method, data synchronization circuit, and data synchronization method |
Mar. 4, 2008 |
| 7337376 |
Method and system of self-test for a single infrared machine |
Feb. 26, 2008 |
| 7331004 |
Data storage system analyzer having self reset |
Feb. 12, 2008 |
| 7324392 |
ROM-based memory testing |
Jan. 29, 2008 |
| 7313753 |
Detector for detecting information carried by a signal having a sawtooth-like shape |
Dec. 25, 2007 |
| 7313738 |
System and method for system-on-chip interconnect verification |
Dec. 25, 2007 |
| 7280420 |
Data compression read mode for memory testing |
Oct. 9, 2007 |
| 7274611 |
Method and architecture to calibrate read operations in synchronous flash memory |
Sep. 25, 2007 |
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