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Class Information
Number: 714/50
Name: Error detection/correction and fault detection/recovery > Data processing system error or fault handling > Reliability and availability > Error detection or notification > State error (i.e., content of instruction, data, or message) > State out of sequence
Description: Subject matter wherein an ordering of state information related to a succession of data, instructions etc., is the basis for state analysis.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7610518 |
Program counter range comparator with equality, greater than, less than and non-equal detection modes |
Oct. 27, 2009 |
| 7594146 |
Apparatus, method, and program for correcting time of event trace data |
Sep. 22, 2009 |
| 7590911 |
Apparatus and method for testing and debugging an integrated circuit |
Sep. 15, 2009 |
| 7586952 |
Packet transmission system, packet transmission method, data reception system, and data reception method |
Sep. 8, 2009 |
| 7555569 |
Quick configuration status |
Jun. 30, 2009 |
| 7533304 |
Method and system of signal noise reduction |
May. 12, 2009 |
| 7523353 |
Method for detecting hang or dead lock conditions |
Apr. 21, 2009 |
| 7428674 |
Monitoring the state vector of a test access port |
Sep. 23, 2008 |
| 7386411 |
Automatic hi-pot test apparatus and method |
Jun. 10, 2008 |
| 7363541 |
Command management using task attributes |
Apr. 22, 2008 |
| 7320093 |
Storage apparatus |
Jan. 15, 2008 |
| 7302477 |
Administration tool for gathering information about systems and applications including the feature of high availability |
Nov. 27, 2007 |
| 7260744 |
Computer system diagnosis with user-developed procedure |
Aug. 21, 2007 |
| 7197561 |
Method and apparatus for maintaining the status of objects in computer networks using virtual state machines |
Mar. 27, 2007 |
| 7162666 |
Multi-processor system having a watchdog for interrupting the multiple processors and deferring preemption until release of spinlocks |
Jan. 9, 2007 |
| 7117398 |
Program counter range comparator with equality, greater than, less than and non-equal detection modes |
Oct. 3, 2006 |
| 7079934 |
Set of peripheral chips |
Jul. 18, 2006 |
| 7076711 |
Automatic testing of microprocessor bus integrity |
Jul. 11, 2006 |
| 7051245 |
System and method for handling out-of-order data supplied by a real-time feed |
May. 23, 2006 |
| 6915456 |
Apparatus and method of diagnosing network protocol errors using XML documents |
Jul. 5, 2005 |
| 6898563 |
System for aiding in the design of combinatorial logic and sequential state machines |
May. 24, 2005 |
| 6880061 |
System and method for monitoring data, computer program and data storage therefor |
Apr. 12, 2005 |
| 6594786 |
Fault tolerant high availability meter |
Jul. 15, 2003 |
| 6543012 |
Method of detecting incorrect sequences of code execution |
Apr. 1, 2003 |
| 6487676 |
Validation of procedures |
Nov. 26, 2002 |
| 6412084 |
Control of computer peripherals |
Jun. 25, 2002 |
| 6412062 |
Injection control mechanism for external events |
Jun. 25, 2002 |
| 6339832 |
Exception response table in environment services patterns |
Jan. 15, 2002 |
| 6237059 |
Method for estimating statistics of properties of memory system interactions among contexts in a computer system |
May. 22, 2001 |
| 6148345 |
Power savings for sound system |
Nov. 14, 2000 |
| 6148421 |
Error detection and recovery for sequential access devices in a fibre channel protocol |
Nov. 14, 2000 |
| 6055598 |
Arrangement and method for allowing sequence-independent command responses across a computer bus bridge |
Apr. 25, 2000 |
| 6021456 |
Method for communicating interrupt data structure in a multi-processor computer system |
Feb. 1, 2000 |
| 5903717 |
Fault tolerant computer system |
May. 11, 1999 |
| 5884101 |
Apparatus for detecting data buffer faults |
Mar. 16, 1999 |
| 5838898 |
Microprogram controlled data processing system having a runaway monitor function |
Nov. 17, 1998 |
| 5761407 |
Message based exception handler |
Jun. 2, 1998 |
| 5758051 |
Method and apparatus for reordering memory operations in a processor |
May. 26, 1998 |
| 5751946 |
Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor |
May. 12, 1998 |
| 5740360 |
Apparatus and method for resetting a microprocessor in the event of improper program execution |
Apr. 14, 1998 |
| 5717849 |
System and procedure for early detection of a fault in a chained series of control blocks |
Feb. 10, 1998 |
| 5706280 |
Transmission quality monitoring system for a digital communication network |
Jan. 6, 1998 |
| 5694542 |
Time-triggered communication control unit and communication method |
Dec. 2, 1997 |
| 5689430 |
Internal state determining apparatus |
Nov. 18, 1997 |
| 5682388 |
Data testing |
Oct. 28, 1997 |
| 5664138 |
Apparatus for handling out-of-order exceptions in pipe-lined parallel processing that prevents execution of all instructions behind exception predicted instruction and aborts if exception actu |
Sep. 2, 1997 |
| 5577200 |
Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system |
Nov. 19, 1996 |
| 5574928 |
Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments |
Nov. 12, 1996 |
| 5559992 |
Apparatus and method for protecting data in a memory address range |
Sep. 24, 1996 |
| 5550975 |
Disk array controller |
Aug. 27, 1996 |
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