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Class Information
Number: 714/32
Name: Error detection/correction and fault detection/recovery > Data processing system error or fault handling > Reliability and availability > Fault locating (i.e., diagnosis or testing) > Particular stimulus creation
Description: Subject matter further including means or steps for selection or generation of a signal (i.e., data) for testing or diagnosing.


Sub-classes under this class:

Class Number Class Name Patents
714/33 Derived from analysis (e.g., of a specification or by stimulation) 334
714/34 Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping) 285
714/35 Substituted or added instruction (e.g., code instrumenting, breakpoint instruction) 277
714/36 Test sequence at power-up or initialization 327


Patents under this class:
1 2 3 4 5

Patent Number Title Of Patent Date Issued
7620861 Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels Nov. 17, 2009
7617431 Method and apparatus for analyzing delay defect Nov. 10, 2009
7596731 Test time reduction algorithm Sep. 29, 2009
7568127 Signal drive de-emphasis control for serial bus Jul. 28, 2009
7555689 Generating responses to patterns stimulating an electronic circuit with timing exception paths Jun. 30, 2009
7548820 Detecting a failure condition in a system using three-dimensional telemetric impulsional response surfaces Jun. 16, 2009
7546397 Systems and methods for allowing multiple devices to share the same serial lines Jun. 9, 2009
7546490 Control system, and program product employing an embedded mechanism for testing a system's fault-handling capability Jun. 9, 2009
7543184 System and method for distributing system tests in parallel computing environments Jun. 2, 2009
7543185 Debug system with event-based virtual processing agents Jun. 2, 2009
7543275 Mechanism for executing test suites written for different harnesses under one test execution harness Jun. 2, 2009
7533294 Functional coverage driven test generation for validation of pipelined processors May. 12, 2009
7529980 Method and apparatus for injecting errors into SAS domains through SAS expanders May. 5, 2009
7526680 Stress testing a website having a backend application Apr. 28, 2009
7519864 Automation test systems Apr. 14, 2009
7516376 Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product Apr. 7, 2009
7516374 Testing circuit and related method of injecting a time jitter Apr. 7, 2009
7502966 Testcase generation via a pool of parameter files Mar. 10, 2009
7500148 Test apparatus and testing method Mar. 3, 2009
7480824 Method for controlling starting operation of unit and executing self-checking test Jan. 20, 2009
7480882 Measuring and predicting VLSI chip reliability and failure Jan. 20, 2009
7475164 Apparatus, system, and method for automated device configuration and testing Jan. 6, 2009
7467068 Method and apparatus for detecting dependability vulnerabilities Dec. 16, 2008
7457987 Test vector manager, method of managing test vectors and a test tool employing the manager and the method Nov. 25, 2008
7453992 System and method for management of call data using a vector based model and relational data structure Nov. 18, 2008
7451350 Object oriented scaleable test executive Nov. 11, 2008
7447966 Hardware verification scripting Nov. 4, 2008
7444558 Programmable measurement mode for a serial point to point link Oct. 28, 2008
7425896 Tag testing device, tag testing method, and tag testing program Sep. 16, 2008
7401259 System and method for scenario generation in a distributed system Jul. 15, 2008
7386763 Proactive systemic scheduler for resource limited test systems Jun. 10, 2008
7366951 Method and apparatus for test program generation based on an instruction set description of a processor Apr. 29, 2008
7352486 Printer Apr. 1, 2008
7353430 Device for validating an integrated circuit Apr. 1, 2008
7353474 System and method for accessing signals of a user design in a programmable logic device Apr. 1, 2008
7315973 Method and apparatus for choosing tests for simulation and associated algorithms and hierarchical bipartite graph data structure Jan. 1, 2008
7290187 Segmented algorithmic pattern generator Oct. 30, 2007
7287189 I/O configuration and reconfiguration trigger through testing interface Oct. 23, 2007
7287242 Efficient re-validation of modified software Oct. 23, 2007
7287190 Simultaneous execution of test suites on different platforms Oct. 23, 2007
7284159 Fault injection method and system Oct. 16, 2007
7269756 Customizable event creation logic for hardware monitoring Sep. 11, 2007
7260760 Method and apparatus to disable compaction of test responses in deterministic test-set embedding-based BIST Aug. 21, 2007
7249285 Address watch breakpoints in a hardware synchronization range Jul. 24, 2007
7243268 Sequential coordination of test execution and dynamic data Jul. 10, 2007
7240243 System and method for facilitating programmable coverage domains for a testcase generator Jul. 3, 2007
7231553 System and method for testing computing devices Jun. 12, 2007
7231571 Single-pass methods for generating test patterns for sequential circuits Jun. 12, 2007
7222260 Test system for medical systems May. 22, 2007
7219314 Application-specific methods for testing molectronic or nanoscale devices May. 15, 2007

1 2 3 4 5


 
 
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