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Class Information
Number: 714
Name: Error detection/correction and fault detection/recovery >
Description: This class provides for process or apparatus for detecting and correcting errors in electrical pulse or pulse coded data.










Class Number Class Name No. of Patents
714/100

Data processing system error or fault handling

335
714/1

Reliability and availability

667
714/48

Error detection or notification

1929
714/57

Error forwarding and presentation (e.g., operator console, error display)

733
714/49

State error (i.e., content of instruction, data, or message)

497
714/53

Address error

185
714/50

State out of sequence

110
714/51

Control flow state sequence monitored (e.g., watchdog processor for control-flow checking)

230
714/52

Error checking code

395
714/54

Storage content error

481
714/55

Timing error (e.g., watchdog timer time-out)

532
714/56

Bus or i/o channel device fault

302
714/25

Fault locating (i.e., diagnosis or testing)

2126
714/37

Analysis (e.g., of output, state, or design)

929
714/39

Monitor recognizes sequence of events (e.g., protocol or logic state analyzer)

756
714/38

Of computer software

1687
714/26

Artificial intelligence (e.g., diagnostic expert system)

636
714/40

Component dependent technique

172
714/43

Bus, i/o channel, or network path component fault

1255
714/41

For reliability enhancing component (e.g., testing backup spare, or fault injection)

219
714/42

Memory or storage device component fault

1290
714/44

Peripheral device component fault

358
714/46

Operator interface for diagnosing or testing

695
714/45

Output recording (e.g., signature or trace)

882
714/27

Particular access structure

422
714/31

Additional processor for in-system fault locating (e.g., distributed diagnosis program)

470
714/30

Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)

1420
714/28

Substituted emulative component (e.g., emulator microprocessor)

279
714/29

Memory emulator feature

107
714/32

Particular stimulus creation

349
714/33

Derived from analysis (e.g., of a specification or by stimulation)

467
714/34

Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping)

368
714/35

Substituted or added instruction (e.g., code instrumenting, breakpoint instruction)

361
714/36

Test sequence at power-up or initialization

505
714/2

Fault recovery

1131
714/3

By masking or reconfiguration

480
714/5

Of memory or peripheral subsystem

1204
714/9

Access processor affected (e.g., i/o processor, mmu, dma processor)

200
714/8

Isolating failed storage location (e.g., sector remapping)

582
714/6

Redundant stored data accessed (e.g., duplicated data, error correction coded data, or other parity-type data)

2581
714/7

Reconfiguration (e.g., adding a replacement storage component)

895
714/4

Of network

1957
714/14

Of power supply

413
714/10

Of processor

763
714/11

Concurrent, redundantly operating processors

981
714/12

Synchronization maintenance of processors

511
714/13

Prepared backup processor (e.g., initializing cold backup) or updating backup processor (e.g., by checkpoint message)

839
714/23

Resetting processor

421
714/24

Safe shutdown

347
714/15

State recovery (i.e., process or data file)

1391
714/16

Forward recovery (e.g., redoing committed action)

350
714/17

Reexecuting single instruction or bus cycle

136
714/20

Plural recovery data sets containing set interrelation data (e.g., time values or log record numbers)

550
714/21

State validity check

208
714/18

Transmission data record (e.g., for retransmission)

320
714/19

Undo record

201
714/22

With power supply status monitoring

509
714/47

Performance monitoring for fault avoidance

1498
 

Diagnostic testing (371/15.1)

 
 

Digital data error correction (371/30)

 
 

Digital logic testing (371/22.1)

 
 

Replacement with spare device or system (371/8.1)

 
 

Memory testing (371/21.1)

 
714/699

Pulse or data error handling

92
714/701

Data formatting to improve error detection correction capability

665
714/702

Memory access (e.g., address permutation)

272
714/709

Data pulse evaluation/bit decision

193
714/746

Digital data error correction

1036
714/752

Forward correction by block code

1515
714/774

Adaptive error-correcting capability

694
714/762

Burst error correction

421
714/781

Code based on generator polynomial

659
714/782

Bose-chaudhuri-hocquenghem code

180
714/783

Golay code

47
714/784

Reed-solomon code

832
714/785

Syndrome computed

527
714/755

Double encoding codes (e.g., product, concatenated)

1556
714/756

Cross-interleave reed-solomon code (circ)

336
714/753

Double error correcting with single error correcting code

135
714/758

Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity)

2104
714/754

Error correction during refresh cycle

106
714/776

For packet or frame multiplexed data

895
714/777

Hamming code

194
714/759

Look-up table encoding or decoding

243
714/763

Memory access

1236
714/766

Check bits stored in separate area of memory

375
714/767

Code word for plural n-bit (n>1) storage units (e.g., x4 dram's)

149
714/772

Code word parallel access

68
714/769

Dynamic data storage

506
714/770

Disk array

348
714/771

Tape

84
714/764

Error correct and restore

485
714/768

Error correction code for memory address

240
714/765

Error pointer

165
714/773

Solid state memory

426
714/778

Nonbinary data (e.g., ternary)

62
714/757

Parallel generation of check bits

219
714/761

Random and burst error correction

227
714/775

Synchronization

312
714/760

Threshold decoding (e.g., majority logic)

109
714/780

Using symbol reliability information (e.g., soft decision)

496
714/779

Variable length data

150
714/786

Forward error correction by tree code (e.g., convolutional)

1041
714/796

Branch metric calculation

554
714/788

Burst error

218
714/794

Maximum likelihood

850
714/790

Puncturing

397
714/787

Random and burst errors

96
714/791

Sequential decoder (e.g., fano or stack algorithm)

75
714/789

Synchronization

142
714/793

Syndrome decodable (e.g., self orthogonal)

78
714/792

Trellis code

657
714/795

Viterbi decoding

1245
714/797

Majority decision/voter circuit

266
714/748

Request for retransmission

1432
714/750

Feedback to transmitter for comparison

258
714/751

Including forward error correction capability

528
714/749

Retransmission if no ack returned

624
714/747

Substitution of previous valid data

252
714/724

Digital logic testing

2375
714/733

Built-in testing circuit (bilbo)

1557
714/745

Determination of marginal operation limits

260
714/736

Device response compared to expected fault-free response

894
714/737

Device response compared to fault dictionary/truth table

114
714/735

Device response compared to input pattern

383
714/738

Including test pattern generator

1099
714/743

Addressing

162
714/744

Clock or synchronization

478
714/740

Having analog signal

92
714/739

Random pattern generation (includes pseudorandom pattern)

309
714/741

Simulation

405
714/742

Testing specific device

524
714/725

Programmable logic array (pla) testing

420
714/726

Scan path testing (e.g., level sensitive scan design (lssd))

1605
714/730

Addressing

102
714/727

Boundary scan

994
714/731

Clock or synchronization

694
714/729

Plural scan paths

727
714/728

Random pattern generation (includes pseudorandom pattern)

241
714/732

Signature analysis

440
714/734

Structural (in-circuit test)

746
714/704

Error count or rate

934
714/705

Pseudo-error rate

58
714/708

Shutdown or establishing system parameter (e.g., transmission rate)

276
714/707

Synchronization control

225
714/706

Up-down counter

68
714/798

Error detection for synchronization control

420
714/799

Error/fault detection technique

777
714/807

Check character

464
714/808

Modulo-n residue check character

70
714/809

Code constraint monitored

105
714/810

Multilevel coding (n>2)

71
714/819

Comparison of data

481
714/824

Device output compared to input

98
714/820

Plural parallel devices of channels

198
714/821

Transmission facility

171
714/822

Sequential repetition

143
714/823

True and complement data

58
714/806

Constant-ratio code (m/n)

37
714/811

Forbidden combination or improper condition

158
714/814

Data timing/clocking

227
714/818

Missing-bit/drop-out detection

64
714/817

Noise level

36
714/812

Specified digital signal or pulse count

95
714/815

Time delay/interval monitored

239
714/813

Two key-down detector

10
714/816

Two-rail logic

22
714/800

Parity bit

636
714/802

Even and odd parity

76
714/801

Parity generator or checker circuit detail

450
714/803

Parity prediction

49
714/804

Plural dimension parity check

161
714/805

Storage accessing (e.g., address parity check)

432
714/718

Memory testing

2439
714/721

Electrical parameter (e.g., threshold voltage)

314
714/723

Error mapping or logging

615
714/722

Performing arithmetic function on memory contents

110
714/719

Read-in with read-out and compare

838
714/720

Special test pattern (e.g., checkerboard, walking ones)

272
714/710

Replacement of memory spare location, portion, or segment

813
714/711

Spare row or column

357
714/700

Skew detection correction

512
714/703

Testing of error-check system

271
714/712

Transmission facility testing

697
714/714

By tone signal

51
714/713

For channel having repeater

78
714/717

Loop or ring configuration

137
714/715

Test pattern with comparison

358
714/716

Loop-back

262
 
 
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