Data processing system error or fault handling

Reliability and availability

Error detection or notification

Error forwarding and presentation (e.g., operator console, error display)

State error (i.e., content of instruction, data, or message)

Address error

State out of sequence

Control flow state sequence monitored (e.g., watchdog processor for control-flow checking)

Error checking code

Storage content error

Timing error (e.g., watchdog timer time-out)

Bus or i/o channel device fault

Fault locating (i.e., diagnosis or testing)

Analysis (e.g., of output, state, or design)

Monitor recognizes sequence of events (e.g., protocol or logic state analyzer)

Of computer software

Artificial intelligence (e.g., diagnostic expert system)

Component dependent technique

Bus, i/o channel, or network path component fault

For reliability enhancing component (e.g., testing backup spare, or fault injection)

Memory or storage device component fault

Peripheral device component fault

Operator interface for diagnosing or testing

Output recording (e.g., signature or trace)

Particular access structure

Additional processor for in-system fault locating (e.g., distributed diagnosis program)

Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)

Substituted emulative component (e.g., emulator microprocessor)

Memory emulator feature

Particular stimulus creation

Derived from analysis (e.g., of a specification or by stimulation)

Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping)

Substituted or added instruction (e.g., code instrumenting, breakpoint instruction)

Test sequence at power-up or initialization

Fault recovery

By masking or reconfiguration

Of memory or peripheral subsystem

Access processor affected (e.g., i/o processor, mmu, dma processor)

Isolating failed storage location (e.g., sector remapping)

Redundant stored data accessed (e.g., duplicated data, error correction coded data, or other parity-type data)

Reconfiguration (e.g., adding a replacement storage component)

Of network

Of power supply

Of processor

Concurrent, redundantly operating processors

Synchronization maintenance of processors

Prepared backup processor (e.g., initializing cold backup) or updating backup processor (e.g., by checkpoint message)

Resetting processor

Safe shutdown

State recovery (i.e., process or data file)

Forward recovery (e.g., redoing committed action)

Reexecuting single instruction or bus cycle

Plural recovery data sets containing set interrelation data (e.g., time values or log record numbers)

State validity check

Transmission data record (e.g., for retransmission)

Undo record

With power supply status monitoring

Performance monitoring for fault avoidance

Diagnostic testing (371/15.1)

Digital data error correction (371/30)

Digital logic testing (371/22.1)

Replacement with spare device or system (371/8.1)

Memory testing (371/21.1)

Pulse or data error handling

Data formatting to improve error detection correction capability

Memory access (e.g., address permutation)

Data pulse evaluation/bit decision

Digital data error correction

Forward correction by block code

Adaptive error-correcting capability

Burst error correction

Code based on generator polynomial

Bose-chaudhuri-hocquenghem code

Golay code

Reed-solomon code

Syndrome computed

Double encoding codes (e.g., product, concatenated)

Cross-interleave reed-solomon code (circ)

Double error correcting with single error correcting code

Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity)

Error correction during refresh cycle

For packet or frame multiplexed data

Hamming code

Look-up table encoding or decoding

Memory access

Check bits stored in separate area of memory

Code word for plural n-bit (n>1) storage units (e.g., x4 dram's)

Code word parallel access

Dynamic data storage

Disk array

Tape

Error correct and restore

Error correction code for memory address

Error pointer

Solid state memory

Nonbinary data (e.g., ternary)

Parallel generation of check bits

Random and burst error correction

Synchronization

Threshold decoding (e.g., majority logic)

Using symbol reliability information (e.g., soft decision)

Variable length data

Forward error correction by tree code (e.g., convolutional)

Branch metric calculation

Burst error

Maximum likelihood

Puncturing

Random and burst errors

Sequential decoder (e.g., fano or stack algorithm)

Synchronization

Syndrome decodable (e.g., self orthogonal)

Trellis code

Viterbi decoding

Majority decision/voter circuit

Request for retransmission

Feedback to transmitter for comparison

Including forward error correction capability

Retransmission if no ack returned

Substitution of previous valid data

Digital logic testing

Built-in testing circuit (bilbo)

Determination of marginal operation limits

Device response compared to expected fault-free response

Device response compared to fault dictionary/truth table

Device response compared to input pattern

Including test pattern generator

Addressing

Clock or synchronization

Having analog signal

Random pattern generation (includes pseudorandom pattern)

Simulation

Testing specific device

Programmable logic array (pla) testing

Scan path testing (e.g., level sensitive scan design (lssd))

Addressing

Boundary scan

Clock or synchronization

Plural scan paths

Random pattern generation (includes pseudorandom pattern)

Signature analysis

Structural (in-circuit test)

Error count or rate

Pseudo-error rate

Shutdown or establishing system parameter (e.g., transmission rate)

Synchronization control

Up-down counter

Error detection for synchronization control

Error/fault detection technique

Check character

Modulo-n residue check character

Code constraint monitored

Multilevel coding (n>2)

Comparison of data

Device output compared to input

Plural parallel devices of channels

Transmission facility

Sequential repetition

True and complement data

Constant-ratio code (m/n)

Forbidden combination or improper condition

Data timing/clocking

Missing-bit/drop-out detection

Noise level

Specified digital signal or pulse count

Time delay/interval monitored

Two key-down detector

Two-rail logic

Parity bit

Even and odd parity

Parity generator or checker circuit detail

Parity prediction

Plural dimension parity check

Storage accessing (e.g., address parity check)

Memory testing

Electrical parameter (e.g., threshold voltage)

Error mapping or logging

Performing arithmetic function on memory contents

Read-in with read-out and compare

Special test pattern (e.g., checkerboard, walking ones)

Replacement of memory spare location, portion, or segment

Spare row or column

Skew detection correction

Testing of error-check system

Transmission facility testing

By tone signal

For channel having repeater

Loop or ring configuration

Test pattern with comparison

Loop-back