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Class Information
Number: 713/503
Name: Electrical computers and digital processing systems: support > Clock, pulse, or timing signal generation or analysis > Correction for skew, phase, or rate
Description: Subject matter wherein a timing interval is corrected for skew or phase, or a rate is corrected by adjustment or alignment.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8713298 Fast and compact circuit for bus inversion Apr. 29, 2014
8707001 Method and system for measuring memory access time using phase detector Apr. 22, 2014
8694670 Time synchronization of multiple time-based data streams with independent clocks Apr. 8, 2014
8689036 Systems and methods for synchronizing operations among a plurality of independently clocked digital data processing devices without a voltage controlled crystal oscillator Apr. 1, 2014
8683253 Optimized synchronous strobe transmission mechanism Mar. 25, 2014
8677173 Method and circuit for trimming an internal oscillator of a USB device Mar. 18, 2014
8677171 Method for controlling the dynamic power signature of a circuit Mar. 18, 2014
8677170 Method for generating a clock signal Mar. 18, 2014
8671304 Adjustment of write timing based on a training signal Mar. 11, 2014
8671305 Techniques for adjusting periodic signals based on data detection Mar. 11, 2014
8667316 Precision synchronisation architecture for superspeed universal serial bus devices Mar. 4, 2014
8656207 Method for modeling variation in a feedback loop of a phase-locked loop Feb. 18, 2014
8631268 Slave device, system including master device and slave device, method for operating the same, and chip package Jan. 14, 2014
8631267 Adjustable byte lane offset for memory module to reduce skew Jan. 14, 2014
8631266 Semiconductor memory device and method of controlling the same Jan. 14, 2014
8619935 Methods and structure for on-chip clock jitter testing and analysis Dec. 31, 2013
8621109 Adaptable management in sync engines Dec. 31, 2013
8615675 Image forming apparatus Dec. 24, 2013
8606989 Methods and apparatus for burst data transfers between double data rate (DDR) memories and embedded processors during training Dec. 10, 2013
8607090 Selective shorting for clock grid during a controlling portion of a clock signal Dec. 10, 2013
8595544 Automatic internal trimming calibration method to compensate process variation Nov. 26, 2013
8595543 Method and circuit for trimming an internal oscillator of a USB device according to a counting number between a first and second clock count value Nov. 26, 2013
8588355 Timing recovery controller and operation method thereof Nov. 19, 2013
8589718 Performance scaling device, processor having the same, and performance scaling method thereof Nov. 19, 2013
8589720 Synchronizing timing mismatch by data insertion Nov. 19, 2013
8578199 Resetting real time clock upon reference clock interruption Nov. 5, 2013
8578200 Conversion of timestamps between multiple entities within a computing system Nov. 5, 2013
8578201 Conversion of timestamps between multiple entities within a computing system Nov. 5, 2013
8572425 Data processing device and mobile device Oct. 29, 2013
8572419 System-on-chip power reduction through dynamic clock frequency Oct. 29, 2013
8554951 Synchronization and ordering of multiple accessess in a distributed system Oct. 8, 2013
8555103 Deskewing apparatus for oscilloscope Oct. 8, 2013
8533521 Method for adjusting phase of a clock in a host based upon comparison of first and second pattern signals from a memory and the first and the second pattern signals pre-stored in the host Sep. 10, 2013
8527803 System and method for multiple backplane time synchronization Sep. 3, 2013
8522066 Providing silicon integrated code for a system Aug. 27, 2013
8516292 Method and apparatus for providing symmetrical output data for a double data rate DRAM Aug. 20, 2013
8516291 Information processing apparatus, data reception device and method of controlling the information processing apparatus Aug. 20, 2013
8510589 Apparatus and method using first and second clocks Aug. 13, 2013
8504862 Device and method for preventing lost synchronization Aug. 6, 2013
8504863 Drift tracking feedback for communication channels Aug. 6, 2013
8504866 Supplying hysteresis effect mitigated clock signals based on silicon-test characterized parameter Aug. 6, 2013
8504867 High resolution clock signal generator Aug. 6, 2013
8504868 Computer system with synchronization/desynchronization controller Aug. 6, 2013
8495410 Sampling phase correcting host controller, semiconductor device and method Jul. 23, 2013
8495409 Host controller, semiconductor device and method for setting sampling phase Jul. 23, 2013
8489911 Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection Jul. 16, 2013
8489912 Command protocol for adjustment of write timing delay Jul. 16, 2013
8477896 Structure for window comparator circuit for clock data recovery from bipolar RZ data Jul. 2, 2013
8473663 Stackable form-factor peripheral component interconnect device and assembly Jun. 25, 2013
8473770 Semiconductor device and data processing system Jun. 25, 2013

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