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Class Information
Number: 713/503
Name: Electrical computers and digital processing systems: support > Clock, pulse, or timing signal generation or analysis > Correction for skew, phase, or rate
Description: Subject matter wherein a timing interval is corrected for skew or phase, or a rate is corrected by adjustment or alignment.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7434082 |
Multi-stage clock selector |
Oct. 7, 2008 |
| 7434078 |
Synchronization with hardware utilizing software clock slaving via a clock |
Oct. 7, 2008 |
| 7430681 |
Methods and apparatus for interfacing a drawing memory with a remote display controller |
Sep. 30, 2008 |
| 7428286 |
Duty cycle correction apparatus and method for use in a semiconductor memory device |
Sep. 23, 2008 |
| 7428654 |
Data transfer circuit for transferring data between a first circuit block and a second circuit block |
Sep. 23, 2008 |
| 7421606 |
DLL phase detection using advanced phase equalization |
Sep. 2, 2008 |
| 7421607 |
Method and apparatus for providing symmetrical output data for a double data rate DRAM |
Sep. 2, 2008 |
| 7418617 |
Apparatus for adjusting timing of memory signals |
Aug. 26, 2008 |
| 7418616 |
System and method for improved synchronous data access |
Aug. 26, 2008 |
| 7415087 |
Circuits with state circuitry having cross connected control inputs |
Aug. 19, 2008 |
| 7412617 |
Phase frequency detector with limited output pulse width and method thereof |
Aug. 12, 2008 |
| 7409574 |
Measuring elapsed time for a software routine |
Aug. 5, 2008 |
| 7406616 |
Data de-skew method and system |
Jul. 29, 2008 |
| 7404099 |
Phase-locked loop having dynamically adjustable up/down pulse widths |
Jul. 22, 2008 |
| 7401246 |
Nibble de-skew method, apparatus, and system |
Jul. 15, 2008 |
| 7398412 |
Measure controlled delay with duty cycle control |
Jul. 8, 2008 |
| 7398413 |
Memory device signaling system and method with independent timing calibration for parallel signal paths |
Jul. 8, 2008 |
| 7398411 |
Self-calibrating time code generator |
Jul. 8, 2008 |
| 7394830 |
System for synchronizing circuitry in an access network |
Jul. 1, 2008 |
| 7392419 |
System and method automatically selecting intermediate power supply voltages for intermediate level shifters |
Jun. 24, 2008 |
| 7383459 |
Apparatus and method for phase-buffering on a bit-by-bit basis using control queues |
Jun. 3, 2008 |
| 7380152 |
Daisy chained multi-device system and operating method |
May. 27, 2008 |
| 7376857 |
Method of timing calibration using slower data rate pattern |
May. 20, 2008 |
| 7376856 |
Circuit arrangement |
May. 20, 2008 |
| 7373541 |
Alignment signal control apparatus and method for operating the same |
May. 13, 2008 |
| 7369623 |
Apparatuses to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit boards |
May. 6, 2008 |
| 7366941 |
Wavefront clock synchronization |
Apr. 29, 2008 |
| 7366939 |
Providing precise timing control between multiple standardized test instrumentation chassis |
Apr. 29, 2008 |
| 7366938 |
Reset in a system-on-chip circuit |
Apr. 29, 2008 |
| 7366937 |
Fast synchronization of a number of digital clocks |
Apr. 29, 2008 |
| 7366940 |
Multiprotocol computer bus interface adapter and method |
Apr. 29, 2008 |
| 7356723 |
Method and apparatus for data transfer |
Apr. 8, 2008 |
| 7356725 |
Method and apparatus for adjusting a time of day clock without adjusting the stepping rate of an oscillator |
Apr. 8, 2008 |
| 7353420 |
Circuit and method for generating programmable clock signals with minimum skew |
Apr. 1, 2008 |
| 7353419 |
Apparatus and method to balance set-up and hold times |
Apr. 1, 2008 |
| 7353418 |
Method and apparatus for updating serial devices |
Apr. 1, 2008 |
| 7350096 |
Circuit to reduce power supply fluctuations in high frequency/ high power circuits |
Mar. 25, 2008 |
| 7346794 |
Method and apparatus for providing clocking phase alignment in a transceiver system |
Mar. 18, 2008 |
| 7346795 |
Delaying lanes in order to align all lanes crossing between two clock domains |
Mar. 18, 2008 |
| 7346798 |
Circuit and method for aligning transmitted data by adjusting transmission timing for plurality of lanes |
Mar. 18, 2008 |
| 7343510 |
Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals |
Mar. 11, 2008 |
| 7340632 |
Domain crossing device |
Mar. 4, 2008 |
| 7340635 |
Register-based de-skew system and method for a source synchronous receiver |
Mar. 4, 2008 |
| 7340631 |
Drift-tolerant sync pulse circuit in a sync pulse generator |
Mar. 4, 2008 |
| 7340630 |
Multiprocessor system with interactive synchronization of local clocks |
Mar. 4, 2008 |
| 7337345 |
Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal |
Feb. 26, 2008 |
| 7337347 |
Information processing system and method for timing adjustment |
Feb. 26, 2008 |
| 7334152 |
Clock switching circuit |
Feb. 19, 2008 |
| 7334148 |
Optimization of integrated circuit device I/O bus timing |
Feb. 19, 2008 |
| 7330604 |
Model-based dewarping method and apparatus |
Feb. 12, 2008 |
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