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Class Information
Number: 713/503
Name: Electrical computers and digital processing systems: support > Clock, pulse, or timing signal generation or analysis > Correction for skew, phase, or rate
Description: Subject matter wherein a timing interval is corrected for skew or phase, or a rate is corrected by adjustment or alignment.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620836 |
Technique for synchronizing network devices in an access data network |
Nov. 17, 2009 |
| 7620837 |
Data transmission system and data transmission apparatus |
Nov. 17, 2009 |
| 7620839 |
Jitter tolerant delay-locked loop circuit |
Nov. 17, 2009 |
| 7617409 |
System for checking clock-signal correspondence |
Nov. 10, 2009 |
| 7617410 |
Simultaneously updating logical time of day (TOD) clocks for multiple cpus in response to detecting a carry at a pre-determined bit position of a physical clock |
Nov. 10, 2009 |
| 7610503 |
Methods for generating a delayed clock signal |
Oct. 27, 2009 |
| 7610504 |
Semiconductor integrated circuit |
Oct. 27, 2009 |
| 7600144 |
Data transmission error reduction via automatic data sampling timing adjustment |
Oct. 6, 2009 |
| 7599459 |
Receiving apparatus, data transmission system and receiving method |
Oct. 6, 2009 |
| 7600145 |
Clustered variations-aware architecture |
Oct. 6, 2009 |
| 7590789 |
Optimizing clock crossing and data path latency |
Sep. 15, 2009 |
| 7584310 |
Signal processing device |
Sep. 1, 2009 |
| 7571340 |
Eliminating receiver clock drift caused by voltage and temperature change in a high-speed I/O system that uses a forwarded clock |
Aug. 4, 2009 |
| 7571339 |
Clock recovery system with triggered phase error measurement |
Aug. 4, 2009 |
| 7571338 |
Determining a time difference between first and second clock domains |
Aug. 4, 2009 |
| 7571267 |
Core clock alignment circuits that utilize clock phase learning operations to achieve accurate clocking of data derived from serial data streams having different relative skews |
Aug. 4, 2009 |
| 7568118 |
Deterministic operation of an input/output interface |
Jul. 28, 2009 |
| 7562246 |
Phase controllable multichannel signal generator |
Jul. 14, 2009 |
| 7562247 |
Providing independent clock failover for scalable blade servers |
Jul. 14, 2009 |
| 7558979 |
Methods for determining simultaneous switching induced data output timing skew |
Jul. 7, 2009 |
| 7555667 |
Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry |
Jun. 30, 2009 |
| 7555668 |
DRAM interface circuits that support fast deskew calibration and methods of operating same |
Jun. 30, 2009 |
| 7555086 |
Plural circuit selection using role reversing control inputs |
Jun. 30, 2009 |
| 7549074 |
Content deskewing for multichannel synchronization |
Jun. 16, 2009 |
| 7542532 |
Data transmission device and input/output interface circuit |
Jun. 2, 2009 |
| 7543202 |
Test apparatus, adjustment apparatus, adjustment method and adjustment program |
Jun. 2, 2009 |
| 7539802 |
Integrated circuit device and signaling method with phase control based on information in external memory device |
May. 26, 2009 |
| 7533285 |
Synchronizing link delay measurement over serial links |
May. 12, 2009 |
| 7526664 |
Drift tracking feedback for communication channels |
Apr. 28, 2009 |
| 7526666 |
Derived clock synchronization for reduced skew and jitter |
Apr. 28, 2009 |
| 7519139 |
Signal monitoring systems and methods |
Apr. 14, 2009 |
| 7519845 |
Software-based audio rendering |
Apr. 14, 2009 |
| 7519844 |
PVT drift compensation |
Apr. 14, 2009 |
| 7512827 |
Dual module clock supply for CAN communication module |
Mar. 31, 2009 |
| 7509514 |
Method and device for the sampling of digital data in synchronous transmission, with maintenance of binary integrity |
Mar. 24, 2009 |
| 7506193 |
Systems and methods for overcoming part to part skew in a substrate-mounted circuit |
Mar. 17, 2009 |
| 7502815 |
True random number generator and method of generating true random numbers |
Mar. 10, 2009 |
| 7500130 |
Cycle-accurate real-time clocks and methods to operate the same |
Mar. 3, 2009 |
| 7500131 |
Training pattern based de-skew mechanism and frame alignment |
Mar. 3, 2009 |
| 7496781 |
Timing signal generating circuit with a master circuit and slave circuits |
Feb. 24, 2009 |
| 7496780 |
Reduction of data skew in parallel processing circuits |
Feb. 24, 2009 |
| 7493510 |
Clock signal generator circuit for serial bus communication |
Feb. 17, 2009 |
| 7493508 |
Information processing device, method, and program |
Feb. 17, 2009 |
| 7490187 |
Hypertransport/SPI-4 interface supporting configurable deskewing |
Feb. 10, 2009 |
| 7486754 |
System clock distributing apparatus and system clock distributing method |
Feb. 3, 2009 |
| 7487378 |
Asymmetrical IO method and system |
Feb. 3, 2009 |
| 7478255 |
Clock distribution in multi-cell computing systems |
Jan. 13, 2009 |
| 7475272 |
Method for calculating clock offset and skew |
Jan. 6, 2009 |
| 7472305 |
Method and apparatus for limiting the output frequency of an on-chip clock generator |
Dec. 30, 2008 |
| 7469354 |
Circuit including a deskew circuit for asymmetrically delaying rising and falling edges |
Dec. 23, 2008 |
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