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Class Information
Number: 713/500
Name: Electrical computers and digital processing systems: support > Clock, pulse, or timing signal generation or analysis
Description: Subject matter including generation, division or distribution of a clock signal, pulse signal, or timing signal in the digital data processing system from one or more sources into a group of continuous and successive time increments; or including event timing and counting, or correction of a clock signal, pulse signal, or timing signal.


Sub-classes under this class:

Class Number Class Name Patents
713/503 Correction for skew, phase, or rate 679
713/502 Counting, scheduling, or event timing 763
713/501 Multiple or variable intervals or frequencies 869


Patents under this class:

Patent Number Title Of Patent Date Issued
7620862 Method of and system for testing an integrated circuit Nov. 17, 2009
7620839 Jitter tolerant delay-locked loop circuit Nov. 17, 2009
7620788 Memory device sequencer and method supporting multiple memory device clock speeds Nov. 17, 2009
7619449 Method and apparatus for synchronous clock distribution to a plurality of destinations Nov. 17, 2009
7617431 Method and apparatus for analyzing delay defect Nov. 10, 2009
7617410 Simultaneously updating logical time of day (TOD) clocks for multiple cpus in response to detecting a carry at a pre-determined bit position of a physical clock Nov. 10, 2009
7617409 System for checking clock-signal correspondence Nov. 10, 2009
7617339 Serial interface circuit for data transfer Nov. 10, 2009
7613164 Method and apparatus for generating and distributing an internal clock for radio network controller Nov. 3, 2009
7610504 Semiconductor integrated circuit Oct. 27, 2009
7610503 Methods for generating a delayed clock signal Oct. 27, 2009
7610416 Systems and methods for controlling rise and fall times of USB signals Oct. 27, 2009
7610175 Timestamping signal monitor device Oct. 27, 2009
7606952 Method for operating serial flash memory Oct. 20, 2009
7603579 Semiconductor chip and semiconductor integrated circuit device for relaying a reference clock from one hard macro to another Oct. 13, 2009
7600167 Flip-flop, shift register, and scan test circuit Oct. 6, 2009
7600144 Data transmission error reduction via automatic data sampling timing adjustment Oct. 6, 2009
7600143 Method and apparatus for variable delay data transfer Oct. 6, 2009
7600141 Data processing performance control Oct. 6, 2009
7599459 Receiving apparatus, data transmission system and receiving method Oct. 6, 2009
7596711 Method and network for synchronistic processing and providing data using an extrapolation data set including at least one update time point Sep. 29, 2009
7596669 Apparatus and method for managing memory in a network switch Sep. 29, 2009
7590880 Circuitry and method for detecting and protecting against over-clocking attacks Sep. 15, 2009
7590789 Optimizing clock crossing and data path latency Sep. 15, 2009
7587621 Computer system management and throughput maximization in the presence of power constraints Sep. 8, 2009
7581132 System and method for configuring a microcontroller clock system Aug. 25, 2009
7577862 Self adjusting clocks in computer systems that adjust in response to changes in their environment Aug. 18, 2009
7577861 Duty cycle rejecting serializing multiplexer for output data drivers Aug. 18, 2009
7574613 Scaling idle detection metric for power management on computing device Aug. 11, 2009
7573932 Spread spectrum clock generator Aug. 11, 2009
7573914 Systems and methods for synchronizing time across networks Aug. 11, 2009
7571342 Processor system, instruction sequence optimization device, and instruction sequence optimization program Aug. 4, 2009
7571340 Eliminating receiver clock drift caused by voltage and temperature change in a high-speed I/O system that uses a forwarded clock Aug. 4, 2009
7571339 Clock recovery system with triggered phase error measurement Aug. 4, 2009
7571338 Determining a time difference between first and second clock domains Aug. 4, 2009
7571076 Performance monitor device, data collecting method and program for the same Aug. 4, 2009
7570669 Synchronizing packet traces Aug. 4, 2009
7568118 Deterministic operation of an input/output interface Jul. 28, 2009
7565564 Switching circuit and method thereof for dynamically switching host clock signals Jul. 21, 2009
7562537 Method of determining cooling system effectiveness Jul. 21, 2009
7562246 Phase controllable multichannel signal generator Jul. 14, 2009
7562245 Single chip 3D and 2D graphics processor with embedded memory and multiple levels of power controls Jul. 14, 2009
7562244 Method for data signal transfer across different clock-domains Jul. 14, 2009
7558980 Systems and methods for the distribution of differential clock signals to a plurality of low impedance receivers Jul. 7, 2009
7558979 Methods for determining simultaneous switching induced data output timing skew Jul. 7, 2009
7557849 Processor-controlled timing generator for multiple image sensors Jul. 7, 2009
7555670 Clocking architecture using a bidirectional clock port Jun. 30, 2009
7555668 DRAM interface circuits that support fast deskew calibration and methods of operating same Jun. 30, 2009
7555086 Plural circuit selection using role reversing control inputs Jun. 30, 2009
7551739 System and method for container monitoring, real time authentication, anomaly detection, and alerts Jun. 23, 2009



 
 
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