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Class Information
Number: 712/34
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Microprocessor or multichip or multimodule processor having sequential program control > Including coprocessor
Description: Subject matter including an auxiliary processor which provides a supplemental function for or other assistance to a primary processor.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620796 |
System and method for acceleration of streams of dependent instructions within a microprocessor |
Nov. 17, 2009 |
| 7617334 |
Data processing system, data processing method and program |
Nov. 10, 2009 |
| 7613109 |
Processing data for a TCP connection using an offload unit |
Nov. 3, 2009 |
| 7614056 |
Processor specific dispatching in a heterogeneous configuration |
Nov. 3, 2009 |
| 7600096 |
Coprocessor extension architecture built using a novel split-instruction transaction model |
Oct. 6, 2009 |
| 7594097 |
Microprocessor output ports and control of instructions provided therefrom |
Sep. 22, 2009 |
| 7590869 |
On-chip multi-core type tamper resistant microprocessor |
Sep. 15, 2009 |
| 7590823 |
Method and system for handling an instruction not supported in a coprocessor formed using configurable logic |
Sep. 15, 2009 |
| 7590822 |
Tracking an instruction through a processor pipeline |
Sep. 15, 2009 |
| 7587577 |
Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content |
Sep. 8, 2009 |
| 7577822 |
Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization |
Aug. 18, 2009 |
| 7546483 |
Offloading RAID functions to a graphics coprocessor |
Jun. 9, 2009 |
| 7539847 |
Stalling processor pipeline for synchronization with coprocessor reconfigured to accommodate higher frequency operation resulting in additional number of pipeline stages |
May. 26, 2009 |
| 7533238 |
Method for limiting the size of a local storage of a processor |
May. 12, 2009 |
| 7533246 |
Application program execution enhancing instruction set generation for coprocessor and code conversion with marking for function call translation |
May. 12, 2009 |
| 7523449 |
System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture |
Apr. 21, 2009 |
| 7516302 |
Efficient use of co-processor in platform independent instruction machine by controlling result transfer and translation and transfer timing of subsequent instruction based on instruction type |
Apr. 7, 2009 |
| 7502910 |
Sideband scout thread processor for reducing latency associated with a main processor |
Mar. 10, 2009 |
| 7500083 |
Accelerated processing with scheduling to configured coprocessor for molecular data type by service and control coprocessor upon analysis of software code |
Mar. 3, 2009 |
| 7493470 |
Processor apparatus and methods optimized for control applications |
Feb. 17, 2009 |
| 7493471 |
Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready |
Feb. 17, 2009 |
| 7490223 |
Dynamic resource allocation among master processors that require service from a coprocessor |
Feb. 10, 2009 |
| 7490222 |
High and low power dual CPU cardiograph data processing system with gathering an display |
Feb. 10, 2009 |
| 7490221 |
Synchronization between pipelines in a data processing apparatus utilizing a synchronization queue |
Feb. 10, 2009 |
| 7487302 |
Service layer architecture for memory access system and method |
Feb. 3, 2009 |
| 7480786 |
Methods and cores using existing PLD processors to emulate processors having different instruction sets and bus protocols |
Jan. 20, 2009 |
| 7457890 |
Integrated multimedia system |
Nov. 25, 2008 |
| 7444637 |
Systems and methods for scheduling coprocessor resources in a computing system |
Oct. 28, 2008 |
| 7437535 |
Method and apparatus for issuing a command to store an instruction and load resultant data in a microcontroller |
Oct. 14, 2008 |
| 7430652 |
Devices for performing multiple independent hardware acceleration operations and methods for performing same |
Sep. 30, 2008 |
| 7418574 |
Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction |
Aug. 26, 2008 |
| 7411187 |
Ion trap in a semiconductor chip |
Aug. 12, 2008 |
| 7409251 |
Method and system for writing NV memories in a controller architecture, corresponding computer program product and computer-readable storage medium |
Aug. 5, 2008 |
| 7406559 |
In-circuit programming architecture with processor, delegable flash controller, and code generator |
Jul. 29, 2008 |
| 7398368 |
Atomic operation involving processors with different memory transfer operation sizes |
Jul. 8, 2008 |
| 7395409 |
Split embedded DRAM processor |
Jul. 1, 2008 |
| 7395410 |
Processor system with an improved instruction decode control unit that controls data transfer between processor and coprocessor |
Jul. 1, 2008 |
| 7392524 |
Method, system, and storage medium for managing computer processing functions |
Jun. 24, 2008 |
| 7386704 |
Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method |
Jun. 10, 2008 |
| 7386705 |
Method for allocating processor resources and system for encrypting data |
Jun. 10, 2008 |
| 7383424 |
Computer architecture containing processor and decoupled coprocessor |
Jun. 3, 2008 |
| 7379418 |
Method for ensuring system serialization (quiesce) in a multi-processor environment |
May. 27, 2008 |
| 7376812 |
Vector co-processor for configurable and extensible processor architecture |
May. 20, 2008 |
| 7373488 |
Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values |
May. 13, 2008 |
| 7370123 |
Information processing apparatus |
May. 6, 2008 |
| 7363473 |
System for dynamic service provisioning |
Apr. 22, 2008 |
| 7355601 |
System and method for transfer of data between processors using a locked set, head and tail pointers |
Apr. 8, 2008 |
| 7356670 |
Data processing system |
Apr. 8, 2008 |
| 7356676 |
Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register |
Apr. 8, 2008 |
| 7350055 |
Tightly coupled accelerator |
Mar. 25, 2008 |
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